记一记，写一写，就不怕忘了；同时还能帮到别人一点点，是多么快乐的一件事~~~

/****************************Copyright**********************************
**                           CrazyBird 
**               http://blog.chinaaet.com/crazybird
**
**------------------------File Infomation-------------------------------
** FileName     :       name_interface.v
** Author       :       CrazyBird
** Data         :       2015-11-10
** Version      :       v1.0
** Description  :       AXI_LITE Interface
**                      
***********************************************************************/
// synopsys translate_off
`timescale 1 ns / 1 ps
// synopsys translate_on
module  name_interface
#(
    //  parameter definition
    parameter   C_S_AXI_ADDR_WIDTH = 32,
    parameter   C_S_AXI_DATA_WIDTH = 32,
    parameter   C_BASEADDR         = 32'hffff_ffff,
    parameter   C_HIGHADDR         = 32'h0000_0000
)(
    //  global signals
    input                                   S_AXI_ACLK,
    input                                   S_AXI_ARESET,
    //  slave interface write address ports
    input       [C_S_AXI_ADDR_WIDTH-1:0]    S_AXI_AWADDR,
    input                                   S_AXI_AWVALID,
    output                                  S_AXI_AWREADY,
    //  slave interface write data ports
    input       [C_S_AXI_DATA_WIDTH-1:0]    S_AXI_WDATA,
    input       [C_S_AXI_DATA_WIDTH/8-1:0]  S_AXI_WSTRB,
    input                                   S_AXI_WVALID,
    output                                  S_AXI_WREADY,
    //  slave interface write response ports
    output      [1:0]                       S_AXI_BRESP,
    output reg                              S_AXI_BVALID,
    input                                   S_AXI_BREADY,
    //  slave interface read address ports 
    input       [C_S_AXI_ADDR_WIDTH-1:0]    S_AXI_ARADDR,
    input                                   S_AXI_ARVALID,
    output                                  S_AXI_ARREADY,
    //  slave interface read data ports
    output reg  [C_S_AXI_DATA_WIDTH-1:0]    S_AXI_RDATA,
    output      [1:0]                       S_AXI_RRESP,
    output reg                              S_AXI_RVALID,
    input                                   S_AXI_RREADY,
    //  user ports
    output      [7:0]                       led_data
);
//------------------------------------------------------
//  register variable definition
reg     [7:0]       reg0;

//------------------------------------------------------
//  write operation(Don't change)
assign  S_AXI_AWREADY = S_AXI_AWVALID & S_AXI_WVALID;
assign  S_AXI_WREADY  = S_AXI_AWVALID & S_AXI_WVALID;
always @(posedge S_AXI_ACLK or posedge S_AXI_ARESET)
begin
    if(S_AXI_ARESET == 1'b1)
        S_AXI_BVALID <= 1'b0;
    else if((S_AXI_AWVALID & S_AXI_WVALID) == 1'b1)
        S_AXI_BVALID <= 1'b1;
    else if(S_AXI_BREADY == 1'b1)
        S_AXI_BVALID <= 1'b0;
end
assign  S_AXI_BRESP = 2'b00;

//------------------------------------------------------
//  write operation(Modified by the user)
always @(posedge S_AXI_ACLK or posedge S_AXI_ARESET)
begin
    if(S_AXI_ARESET == 1'b1)
    begin
        reg0 <= 8'b0;
    end
    else if((S_AXI_AWVALID & S_AXI_WVALID) == 1'b1)
    begin
        case(S_AXI_AWADDR[2])
            1'b0 : reg0 <= S_AXI_WDATA[7:0];
            default : ;
        endcase
    end
end

//------------------------------------------------------
//  read operation(Don't change)
assign  S_AXI_ARREADY = 1'b1;
always @(posedge S_AXI_ACLK or posedge S_AXI_ARESET)
begin
    if(S_AXI_ARESET == 1'b1)
        S_AXI_RVALID <= 1'b0;
    else if((S_AXI_ARREADY & S_AXI_ARVALID) == 1'b1)
        S_AXI_RVALID <= 1'b1;
    else if(S_AXI_RREADY == 1'b1)
        S_AXI_RVALID <= 1'b0;
end
assign  S_AXI_RRESP = 2'b00;

//------------------------------------------------------
//  read operation(Modified by the user)
always @(posedge S_AXI_ACLK or posedge S_AXI_ARESET)
begin
    if(S_AXI_ARESET == 1'b1)
    begin
        S_AXI_RDATA <= {(C_S_AXI_DATA_WIDTH){1'b0}};
    end
    else if((S_AXI_ARVALID & S_AXI_RVALID) == 1'b1)
    begin
        case(S_AXI_ARADDR[2])
            1'b0 : S_AXI_RDATA <= {24'b0,reg0};
            default : S_AXI_RDATA <= {(C_S_AXI_DATA_WIDTH){1'b0}};
        endcase
    end
end

//------------------------------------------------------
//  user logic
assign  led_data = reg0;

endmodule
//****************************End File**********************************