1、取绝对值

-------------------------------------------------------------------------------
-- Title       : Absolute value for 2's complement numbers
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AbsVal.vhd
-- Author      :
-- Company     :
-- Date        :
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Computes the absolute value using a parallel-prefix 2's complementer.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AbsVal is

  generic (width : positive := 8;   -- word width
       speed : speedType := fast);  -- performance parameter

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
    Z : out std_logic_vector(width-1 downto 0));  -- result

end AbsVal;

-------------------------------------------------------------------------------

architecture Behavioral of AbsVal is

  signal Asgn, Zsgn : signed(width-1 downto 0);  -- signed

begin

  -- type conversion: std_logic_vector -> signed
  Asgn <= signed(A);

  -- complement if A negative
  Zsgn <= 0 - Asgn when Asgn < 0 else
      Asgn;

  -- type conversion: signed -> std_logic_vector
  Z <= std_logic_vector(Zsgn);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AbsVal is

  signal Neg : std_logic;       -- negation enable
  signal AI : std_logic_vector(width downto 0);  -- A inverted
  signal PO : std_logic_vector(width downto 0);  -- prefix propagate out

begin

  -- negation enable is sign (MSB) of A
  Neg <= A(width-1);

  -- invert A for complement and attach carry-in
  AI <= (A xor (width-1 downto 0 => Neg)) & Neg;

  -- calculate prefix output propagate signal
  prefix : PrefixAnd
    generic map (width+1, speed)
    port map (AI, PO);

  -- calculate result bits
  Z <= AI(width downto 1) xor PO(width-1 downto 0);

end Structural;

-------------------------------------------------------------------------------

2、加法器

-------------------------------------------------------------------------------
-- Title       : Parallel-prefix adder
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Add.vhd
-- Author      : Reto Zimmermann  <zimmi@iis.ee.ethz.ch>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Binary adder using parallel-prefix carry-lookahead logic.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity Add is

  generic (width : positive := 8;   -- word width
       speed : speedType := fast);  -- performance parameter

  port (A, B : in std_logic_vector(width-1 downto 0);  -- operands
    S : out std_logic_vector(width-1 downto 0));  -- sum

end Add;

-------------------------------------------------------------------------------

architecture Behavioral of Add is

  signal Auns, Buns, Suns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= unsigned(A);
  Buns <= unsigned(B);

  -- addition
  Suns <= Auns + Buns;

  -- type conversion: unsigned -> std_logic_vector
  S <= std_logic_vector(Suns);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of Add is

  signal GI, PI : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. in
  signal GO, PO : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. out
  signal PT : std_logic_vector(width-1 downto 0);  -- adder propagate temp
  signal Auns, Buns, Suns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- default ripple-carry adder as slow implementation
  addSlow : if speed = slow generate

    -- type conversion: std_logic_vector -> unsigned
    Auns <= unsigned(A);
    Buns <= unsigned(B);

    -- addition
    Suns <= Auns + Buns;

    -- type conversion: unsigned -> std_logic_vector
    S <= std_logic_vector(Suns);

  end generate addSlow;

  -- parallel-prefix adders as medium and fast implementations
  addFast : if speed /= slow generate

    -- calculate prefix input generate/propagate signals
    GI <= A and B;
    PI <= A or B;
    -- calculate adder propagate signals (PT = A xor B)
    PT <= not GI and PI;

    -- calculate prefix output generate/propagate signals
    prefix : PrefixAndOr
      generic map (width, speed)
      port map (GI, PI, GO, PO);

    -- calculate sum bits
    S <= PT xor GO(width-2 downto 0) & '0';

  end generate addFast;

end Structural;

-------------------------------------------------------------------------------

3、带进位/借位加法

-------------------------------------------------------------------------------
-- Title       : Parallel-prefix adder with carry-in, carry-out
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AddC.vhd
-- Author      : Reto Zimmermann  <zimmi@iis.ee.ethz.ch>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Binary adder using parallel-prefix carry-lookahead logic with:
--   - carry-in (CI)
--   - carry-out (CO)
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AddC is

  generic (width : positive := 8;   -- word width
           speed : speedType := fast);  -- performance parameter

  port (A, B : in std_logic_vector(width-1 downto 0);  -- operands
        CI : in std_logic;          -- carry in
        S : out std_logic_vector(width-1 downto 0);  -- sum
        CO : out std_logic);        -- carry out

end AddC;

-------------------------------------------------------------------------------

architecture Behavioral of AddC is

  signal Auns, Buns, CIuns, Suns : unsigned(width downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= conv_unsigned(A, width+1);
  Buns <= conv_unsigned(B, width+1);
  CIuns <= (0 => CI, others => '0');

  -- addition
  Suns <= Auns + Buns + CIuns;

  -- type conversion: unsigned -> std_logic_vector
  S <= std_logic_vector(Suns(width-1 downto 0));
  CO <= Suns(width);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AddC is

  signal GI, PI : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. in
  signal GO, PO : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. out
  signal PT : std_logic_vector(width-1 downto 0);  -- adder propagate temp

begin

  -- calculate prefix input generate/propagate signal (0)
  GI(0) <= (A(0) and B(0)) or (A(0) and CI) or (B(0) and CI);
  PI(0) <= '0';
  -- calculate adder propagate signal (0) (PT = A xor B)
  PT(0) <= A(0) xor B(0);
  -- calculate prefix input generate/propagate signals (1 to width-1)
  preproc : for i in width-1 downto 1 generate
    GI(i) <= A(i) and B(i);
    PI(i) <= A(i) or B(i);
    -- calculate adder propagate signal (1 to width-1) (PT = A xor B)
    PT(i) <= not GI(i) and PI(i);
  end generate preproc;

  -- calculate prefix output generate/propagate signals
  prefix : PrefixAndOr
    generic map (width, speed)
    port map (GI, PI, GO, PO);

  -- calculate sum and carry-out bits
  S <= PT xor GO(width-2 downto 0) & CI;
  CO <= GO(width-1);

end Structural;

-------------------------------------------------------------------------------

4、全一监测

-------------------------------------------------------------------------------
-- Title       : All-ones detector
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AllOneDet.vhd
-- Author      : Reto Zimmermann  <zimmi@iis.ee.ethz.ch>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/29
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Detection of the all-ones vector.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AllOneDet is

  generic (width : positive := 8);      -- word width

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
    Z : out std_logic);     -- all-ones flag

end AllOneDet;

-------------------------------------------------------------------------------

architecture Behavioral of AllOneDet is

  signal Ones : std_logic_vector(width-1 downto 0);  -- ones vector

begin

  -- initialization of ones vector
  Ones <= (others => '1');

  -- all-ones detection
  Z <= '1' when A = Ones else '0';

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AllOneDet is

  signal ZT : std_logic_vector(width-1 downto 0);  -- temp.

begin

  -- all-ones detection
  zeroFlag : RedAnd
    generic map (width)
    port map (A, Z);

end Structural;

-------------------------------------------------------------------------------