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vivado约束文件报错

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'set_property' expects at least one object

报XDC里面的set_property找不到正确的object,这个在vivado后续版本中都显示为警告,一般都是处于object的port名大小写问题。XDC和Verilog都对大小写敏感。建议RTL内部接口定义全部用小写。

错误: set_property PACKAGE_PIN "V7 " [get_ports "CN1_V7 "]

正确: set_property PACKAGE_PIN "V7 " [get_ports "CN1_v7 "]


ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 9 out of 194 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: CN1_t9, CN1_u7, CN1_v7, CN1_v8, CN1_w8, CN1_y6, CN1_y7, CN1_y8, CN1_y9.

ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

在生成bit时报错,这几个很容易能发现跟其他不报错端口的差异,就是引号内引脚定义中多个空格。port名中多个空格是没有问题的。

set_property PACKAGE_PIN "U7 " [get_ports "CN1_u7 "]

set_property PACKAGE_PIN "V7 " [get_ports "CN1_v7 "]

set_property PACKAGE_PIN "T9 " [get_ports "CN1_t9 "]

set_property PACKAGE_PIN "U10" [get_ports "CN1_u10"]

xilinx后来推荐的写法是不带引号,这样你为了对齐而多插几个空格都是OK的。

set_property PACKAGE_PIN U7  [get_ports CN1_u7 ]

set_property PACKAGE_PIN V7  [get_ports CN1_v7 ]

set_property PACKAGE_PIN T9  [get_ports CN1_t9 ]

set_property PACKAGE_PIN U10 [get_ports CN1_u10]



  1. 学习啦!感谢分享

  2. 记录分享好习惯啊