在学习VHDL，写的小代码贴上来吧，备忘。先写一位全加器，然后利用一位全加器搭成四位全加器。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity full_add_1 is 
  port(
        a	:  in  std_logic;
		  b     :  in  std_logic;
		  cin  :  in  std_logic;
		  cout : out std_logic;
		  sum :  out std_logic);
end full_add_1;

architecture behavour of full_add_1 is

begin
  sum  <= ((a xor b)xor cin);
  cout <= (((a xor b)and cin))or(a and b);

end behavour;

library ieee;
use ieee.std_logic_1164.all; 

library work;

entity full_add4 is 
	port
	(
		cin :  in  STD_LOGIC;
		  a :  in  STD_LOGIC_VECTOR(3 downto 0);
		  b :  in  STD_LOGIC_VECTOR(3 downto 0);
	  cout :  out  STD_LOGIC;
		sum :  out  STD_LOGIC_VECTOR(3 downto 0)
	);
end full_add4;

architecture bdf_type of full_add4 is 

component full_add_1
	port(a : in STD_LOGIC;
		  b : in STD_LOGIC;
		 cin: in STD_LOGIC;
		cout: out STD_LOGIC;
		 sum: out STD_LOGIC
	);
end component;

signal	cout_wire :  STD_LOGIC_VECTOR(2 downto 0);


begin 

b2v_inst : full_add_1
PORT MAP(a => a(0),
		 b => b(0),
		 cin => cin,
		 cout => cout_wire(0),
		 sum => sum(0));


b2v_inst1 : full_add_1
PORT MAP(a => a(1),
		 b => b(1),
		 cin => cout_wire(0),
		 cout => cout_wire(1),
		 sum => sum(1));


b2v_inst2 :  full_add_1
PORT MAP(a => a(2),
		 b => b(2),
		 cin => cout_wire(1),
		 cout => cout_wire(2),
		 sum => sum(2));


b2v_inst3 :  full_add_1
PORT MAP(a => a(3),
		 b => b(3),
		 cin => cout_wire(2),
		 cout => cout,
		 sum => sum(3));


END bdf_type;


testbench:

library ieee;
use ieee.std_logic_1164.all;

entity full_add4_tb is
end full_add4_tb;

architecture behaviour of full_add4_tb is
  
    component full_add4
	     port (			
				cin :  IN  STD_LOGIC;
	       	  a :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
				  b :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
		     cout :  OUT STD_LOGIC;
		      sum :  OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
	 end component;
	 
     signal 	a: std_logic_vector(3 DOWNTO 0):="0000";
	  signal		b: std_logic_vector(3 DOWNTO 0):="0000";
	  signal  cin: std_logic:='0';
	  signal  sum: std_logic_vector(3 downto 0);
	  signal cout: std_logic;
	
begin
	 
  u1: full_add4 port map(
     a		=>a,
	  b		=>b,
	  cin    =>cin,
	  cout	=>cout,
	  sum 	=>sum);
	  
   process
	  begin  
	     wait for 0  ns; a<="1111";b<="1110";
		  wait for 10 ns; a<="1101";b<="1100";
		  wait for 10 ns; a<="1011";b<="1110";
		  wait for 10 ns; a<="0011";b<="1000";
		  wait for 10 ns; a<="0001";b<="0011";
	
		  wait for 10 ns; 
	  end process;
end behaviour;