module inout_sim(din, clk,ctrl, dout, dinout);
	input [3:0] din;
	input clk;
	input ctrl;
	output reg [3:0] dout;
	inout [3:0] dinout;
	
	reg [3:0]din_reg;
	
	assign dinout=ctrl?din_reg:4'hz;

always @(posedge clk)

	if(ctrl)
	  din_reg<=din;
	else 
     dout<=dinout;

endmodule


`timescale 1 ns/ 1 ns
module inout_sim_tb();

reg clk;
reg ctrl;
reg [3:0] din;
//reg [3:0] treg_dinout;                                              
wire [3:0]  dinout;
wire [3:0]  dout;
                         
//assign dinout = treg_dinout;
inout_sim i1 (
  
	.clk(clk),
	.ctrl(ctrl),
	.din(din),
	.dinout(dinout),
	.dout(dout)
);
initial                                                
begin                                                  
  clk=0;
  ctrl=1;
  din=0;
#20 din=4'h1;
#20 din=4'h2;
#20 din=4'h3;
#20 din=4'h4;

//#100 ctrl=0;
//     treg_dinout=4'h5; 这里是自动生成的testbenchg给出的代码，改成下面的force赋值
//#20  treg_dinout=4'h6;
#100 ctrl=0;
    force  dinout=4'h5; //双向口作为输入时用force进行强制复制
#20 force  dinout=4'h6;//应对testbench中wire型的inout不能复制的问题，结果很好
  
end                                                    
always #10 clk=~clk;                                                
                                                 
endmodule