Simulink HDL Coder——基于模型的FPGA设计
0赞总有一天，FPGA设计将不再是硬件工程师的专利，最优HDL编码的规律将会嵌入到EDA工具之中，FPGA设计输入的抽象层次将会提升到系统级。
Simulink HDL Coder就是这样一款ESL工具（最初在Simulink 2006b中引入），通过它，我们可以一窥FPGA设计的未来。
Recorded Webinar: Rapid FPGA Implementation Using Model-Based Design
进一步了解甚至掌握Simulink HDL Coder还需要学习以下几个工具：
Simulink，基于模型的系统设计输入工具
Integrating MATLAB, Simulink and Stateflow Components in a SimEvents Model
Verifying Embedded MATLAB Functions and Truth Tables in Simulink and Stateflow
Stateflow，状态机输入工具
Recorded Webinar: Introduction to Stateflow
Recorded Webinar: Mealy and Moore Machines in Stateflow
Link for Modelsim，模型和RTL混合仿真工具
Recorded Webinar: HDL Functional Verification with MATLAB & Simulink
Simulink的算法级建模的抽象层次应该略高于SystemC的TLM体系结构级建模的抽象层次，相应地也应该高于SystemVerilog 的TLM建模的抽象层次。从这一点看来，Simulink已经走到了主流EDA工具厂商的前头。
Simulink还支持由模型生成嵌入式C代码。当前存在的问题是，还不支持混合生成C和HDL代码，动态地进行软、硬件功能划分和验证还需要手工 进行。预计不久，就会有第三方设计的DSP+FPGA开发板面市，相应地，软硬件混合建模、代码生成和性能评估工具也会随之一起发售。
相关链接：
20080422 Merging with Agility
20080408 One to Many - FPGA Design Diversifies
20070403 Signal Processing on the Cheap
20070206 Daring DSP
20061114 Team SDR
20060919 Connecting the Camps，Simulink HDL Coder进入EDA市场。The MathWorks Introduces Simulink HDL Coder
20060606 Domesticating DSP
20060117 Erasing the Asterisk
20051115 Assemble All Ye IP
20050809 Platform's Promise
20050308 Plug and Play Design Methodologies for FPGA-based Signal Processing
20041130 Destination DSP
20040824 Methodology Melting Pot
20040727 The Challenges of Modern FPGA Design Verification
20040706 DSP for Less
20040511 DSP Heats Up
20031118 Language Barrier
20031007 Beyond Processors
Creating IP for System Generator for DSP
Efficient Development of Wireless IP with High Level Modeling and ...
FPGA Co-Processing Architectures for Video Compression
