4.2 Common Design Challenges and Mistakes
An FPGA design mistake may be defined as a design that does not achieve the desired ratio of FPGA resource utilization (I/O, logic, memory, hard IP, resource area) and performance (speed/power) implemented within the FPGA device. The number and impact of FPGA design mistakes and oversights may be minimized by developing and consistently following a optimized FPGA design process. The design process should call out design procedures, milestones and design objectives. It should help manage and stabilize the FPGA design cycle. These design challenges most relevant to rapid development that impact the management and development of an FPGA design are listed below.

    At a system engineering level, common mistakes generally occur when adequate design preparation and planning do not occur. The result is an unstable development effort where schedule slips and missed design objectives hamper the success of the project.
    The resulting design failures occurring from these common mistakes impact design efforts and add significant risk. Usually, this haste is brought about by an overly aggressive schedule, a result of wishful thinking brought about by pressure to produce a product meeting unrealistic goals. Designers should avoid common mistakes resulting from aggressive schedule pressure. Following are some common design mistakes to watch for and avoid.

• Starting an FPGA design in earnest before the requirements are sufficiently defined
• System requirement changes that are not "rolled down" to the FPGA requirements
• FPGA requirement updates that are not effectively communicated to the design team
• Too many FPGA requirement changes
• Significant FPGA requirement changes too far into the design cycle
• Allowing too many people to change FPGA design requirements
• Insufficient review of FPGA design change impacts
• Poor or inconsistent HDL coding standard application
• Poor or inconsistent HDL source structure (system architecture)
• Poor or incorrect commenting of HDL source
• Inefficient HDL coding style
• Poor partitioning of design functionality between hardware and software functions
• Poor partitioning of design functionality between fixed-function and programmable design components
• Poor planning for design module and IP function block integration
• Poor planning for design verification (debug & test)
• Poor selection of design tools
• Insufficient / Ineffective training of design team staff
• Poor design documentation
• Not enough design margin (resources, schedule, budget, personnel)
• Poor design team staffing
• Unclear design responsibility assignment
• Allowing the same individual to implement and test a design module
• Over-constraining a design
• Poor or incomplete module-to-module interface within the FPGA device
• Poor or incomplete FPGA to board-level signal and circuitry interface definition
• Incomplete analysis or implementation of pre-configuration I/O signal state for FPGA I/O pins
• Incorrect pin assignments at the FPGA component level
• Incorrect FPGA device footprint signal, power or ground connectivity within the target board PCB
• Overly aggressive design schedule
• Performance requirements too close to the theoretical maximum performance of a family device or technology

4.2 常见的设计挑战和错误

FPGA设计错误可以定义为：在特定的FPGA器件内，没能达到资源利用率（I/O资源、逻辑资源、存储资源、硬IP资源、resource area）和性能（速率/功耗）要求的设计。开发并遵循一个优化的FPGA设计流程，就可以最小化FPGA设计中的错误和疏忽的数量及影响。这一流程应该定义明确的设计步骤、设计阶段目标和设计最终目标。它应该使FPGA设计周期得到管理并稳定下来。下面 列出了与快速系统原型设计最相关的，影响FPGA设计的管理和开发过程的设计挑战。

常见的设计挑战：

< >PCB版图设计PCB信号完整性设计FPGA外部时钟设计FPGA引脚分配设计余量：包 括FPGA逻辑资 源、时钟资源、存储器资源、内嵌处理器资源、性能、开发进度和经费设计预算：包 括逻辑资源、进度计划、开发经费、开发人员的构成和数量设计功能的可 增强和可扩展性设计设计功能的结 构化实现设计功能的确 认和验证常见的设计错误：< >在FPGA设计需求未充分明确的情况下，急迫 地开始FPGA设 计变更后的系统 需求，没能细化为FPGA设计需求更新后的FPGA设计需求，没能有效地传达给设计团 队太多的FPGA设计需求变更在设计过程的 后期提出显著的FPGA设计需求变更允许太多的人 改变FPGA设计 需求对FPGA设计需求变更产生的影响缺乏评审对HDL编码标准的使用欠佳或前后不一致源代码结构 （系统层次结构）欠佳或前后不一致对HDL源代码的注释欠佳或不正确低效率的HDL编码风格硬件与软件之 间的功能划分欠佳固定功能元件 与可编程元件之间的功能划分欠佳IP与系统中其他功能模块的集成计划欠佳设计验证（调 试和测试）计划欠佳设计工具选择 不当对设计团队成 员的培训不充分或效果欠佳设计文档编制 欠佳设计余量（包 括器件资源、开发进度、经费预算、人员配备）预留不充分设计团队成员 构成欠佳设计责任分配 不明确让同一个人对 设计模块进行功能实现和功能验证对设计进行 “过约束”FPGA内部模块之间接口设计欠佳或不完整FPGA与板级信号或电路的接口定义欠佳或不完整对FPGA I/O引脚在配置前的信号电平状 态的分析不完善或处理不当对FPGA I/O引脚位置的分配不正确在目标板上，FPGA 器件封装的信号、电源、地引脚的 连接有误开发进度过于 紧张性能要求太过 于接近某一系列器件或某一器件工艺理论上的最高值