Here is the description of the Avalon VIP Suite and the advantages of using it.

The Avalon Verification IP Suite provides bus functional models (BFMs) to simulate
the behavior of Avalon Memory-Mapped (Avalon-MM) master and slave interfaces
and Avalon Streaming (Avalon-ST) source and sink interfaces. It also provides
monitors to verify both Avalon protocols. This suite facilitates the verification of IP
that includes Avalon-MM and Avalon-ST interfaces. Using the Altera-provided BFMs
and monitors has the following advantages:
■ It accelerates the verification process by providing key components of the
verification testbench.
■ It provides Avalon BFM components that implement the standard Avalon-MM
and Avalon-ST protocols, serving as a reference for those protocols.
■ For SystemVerilog users, it provides a platform that you can use to implement
constraint-driven randomized tests, including traffic scenario drivers, scoreboard
and coverage facilities, and assertion checkers.

Besides of its normal use in verification of a system built with SOPC Builder, the Avalon VIP Suite is a good start point for me to learn the HV features of the SystemVerilog Language and then OVM.
The source code of the VIP Suite is open. So I can dive into the details of its implementation.
First let me start by drawing a MindMap of studying the User Guide.


Sat Mar 13 2010 08:31:11 GMT+0800 (CST) The Fractional Tree of Human Knowledge: The structure of the User Guide.
The Avalon-ST part is not finished yet. The details of the Avalon-MM VIP APIs will be added.

I will run the tutorial simulations next and observe the behavior of the VIP from the outside. After running all the tutorial simualtions, I will try to modify the tutorial testbenches to gain some hands-on experience.


Sat Mar 13 2010 19:45:18 GMT+0800 (CST) The Fractional Tree of Human Knowledge: The structure of the Avalon-MM master BFM testbench.

Sun Mar 14 2010 13:47:08 GMT+0800 (CST) The slave BFM testbench has similar structure with the master BFM testbench.


Sun Mar 14 2010 16:37:59 GMT+0800 (CST) Finished the ST part of the User Guide.

Sun Mar 14 2010 21:03:00 GMT+0800 (CST) The Fractional Tree of Human Knowledge: The structure of the Avalon-ST BFM testbench.