ADI公司的 ADRF6801是集成了分数N PLL和VCO的750MH-1150MHz的高动态围的IQ正交解调器，LO的频率为750MH-1150MHz，输入P1dB为12.5 dBm，噪音（DSB）为14.3dB，电压转换增益为5.1dB。正交解调的相位精度为0.3度，放大精度为0.05 dB，主要用在QAM/QPSK RF/IF解调器，蜂窝W-CDMA/CDMA/CDMA2000，微波点对（多）点无线通信，宽带无线和WiMAX。本文介绍了ADRF6801主要特性，功能方框图，基本连接图和评估板电路图，元件数值和布局图以及通用特性，噪音特性和相位噪音测试框图。

The ADRF6801 is a high dynamic range IQ demodulator with integrated PLL and VCO. The fractional-N PLL/synthesizer generates a frequency in the range of 3.0 GHz to 4.6 GHz. A divide-by-4 quadrature divider divides the output frequency of the VCO down to the required local oscillator (LO) frequency to drive the mixers in quadrature. Additionally, an output buffer can be enabled that generates an fVCO/2 signal for external use.

The PLL reference input is supported from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO.

The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential I and Q output paths have excellent quadrature accuracy and can handle baseband signaling or complex IF up to 120 MHz.

The ADRF6801 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is specified over the −40°C to +85°C temperature range.

ADRF6801主要特性：

IQ demodulator with integrated fractional-N PLL

LO frequency range: 750 MHz to 1150 MHz

Input P1dB: 12.5 dBm

Input IP3: 25 dBm

Noise figure (DSB): 14.3 dB

Voltage conversion gain: 5.1 dB

Quadrature demodulation accuracy

Phase accuracy: 0.3°

Amplitude accuracy: 0.05 dB

Baseband demodulation: 275 MHz, 3 dB bandwidth

SPI serial interface for PLL programming

40-lead, 6 mm × 6 mm LFCSP

ADRF6801应用：

QAM/QPSK RF/IF demodulators

Cellular W-CDMA/CDMA/CDMA2000

Microwave point-to-(multi)point radios

Broadband wireless and WiMAX

 图1。ADRF6801功能方框图

图2。ADRF6801功能描述和引脚配置图

图3。ADRF6801基本连接图

图4。ADRF6801评估板电路图

图5。ADRF6801评估板元件布局图（顶层）
元件数值图：




图6。ADRF6801通用特性测试框图

图7。ADRF6801噪音特性测试框图

图8。ADRF6801相位噪音测试框图