【赛灵思FPGA】[原创]基于Xilinx FPGA的数字跑表实现
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这个项目的主要目的是通过设基于Xilinx FPGA计数字跑表，掌握于Xilinx FPGA的工作原理，掌握动态LED的显示原理，数字跑表的工作原理。
原理：
该跑表有3个输入端，分别为时钟输入（clk）、复位（clr）和启动/暂停（pause）。其结构示意图如下图所示：
复位信号高电平有效，可对整个系统异步清0；当启动/暂停键为低电平时跑表开始计时，为高电平时暂停，变低后在原来的数值基础上再计数。
跑表的计数可以分为以下三个模块：
a．对百分秒进行计数，每计满100，产生一个进位cn1。
b．对秒进行计数，每计满60，产生一个进位cn2。
c．对分钟进行计数，每计满60，系统自动清0。
对所计时间的显示也是本实验的重要组成部分。在此处，我们用了6个LED数码显示管，采用动态扫描的方式进行数字的显示。采用直接位驱动，对应接口：SEL0~SEL3，每一位控制一个LED，悬空为高电平。
源代码
1.Verilog源代码，StopWatch.v
module stopwatch(led_clk, led_rst, led_sel, led_seg, pause);
input led_clk, led_rst, pause;
output reg[3:0] led_sel;
output reg[7:0] led_seg;
integer countsel, countscan;
reg [3:0] led_num1, led_num2, led_num3, led_num4;
reg divclk;
reg run;
parameter ZERO = 8'b11111100,ONE = 8'b01100000, TWO = 8'b11011010;
parameter THREE = 8'b11110010, FOUR =8'b01100110;
parameter FIVE = 8'b10110110, SIX = 8'b10111110, SEVEN =8'b11100000;
parameter EIGHT = 8'b11111110, NINE = 8'b11110110, BLANK = 8'b00000000;
always @(posedge led_clk or negedge led_rst)
begin
if (!led_rst)
begin
countscan = 0;
divclk = 0;
end
else
begin
if (countscan == 99)
begin
countscan = 0;
divclk = ~divclk;
end
else
countscan = countscan + 1;
end
end
always @(posedge divclk or negedge led_rst)
begin
if (!led_rst)
begin
led_num1 = 0;
led_num2 = 0;
led_num3 = 0;
led_num4 = 0;
run = 0;
end
else if (!pause)
run = ~run;
else if(run)
begin
if (led_num1 >= 9)
begin
led_num1 = 0;
if (led_num2 >= 9)
begin
led_num2 = 0;
if (led_num3 >= 9)
begin
led_num3 = 0;
if (led_num4 >= 5)
led_num4 = 0;
else
led_num4 = led_num4 + 1;
end
else
led_num3 = led_num3 + 1;
end
else
led_num2 = led_num2 + 1;
end
else
led_num1 = led_num1 + 1;
end
else
begin
led_num1 = led_num1;
led_num2 = led_num2;
led_num3 = led_num3;
led_num4 = led_num4;
end
end
always @(posedge led_clk or negedge led_rst)
begin
if (!led_rst)
begin
countsel = 0;
led_sel = 4'b0001;
end
else
begin
if (countsel == 4)
begin
countsel =0;
if (led_sel == 4'b1000)
led_sel = 4'b0001;
else
led_sel = led_sel << 1;
end
countsel = countsel + 1;
end
end
always @(led_sel)
begin
case (led_sel)
4'b0001 :
begin
case (led_num1)
0 : led_seg = ZERO;
1 : led_seg = ONE;
2 : led_seg = TWO;
3 : led_seg = THREE;
4 : led_seg = FOUR;
5 : led_seg = FIVE;
6 : led_seg = SIX;
7 : led_seg = SEVEN;
8 : led_seg = EIGHT;
9 : led_seg = NINE;
default : led_seg = BLANK;
endcase
end
4'b0010 :
begin
case (led_num2)
0 : led_seg = ZERO;
1 : led_seg = ONE;
2 : led_seg = TWO;
3 : led_seg = THREE;
4 : led_seg = FOUR;
5 : led_seg = FIVE;
6 : led_seg = SIX;
7 : led_seg = SEVEN;
8 : led_seg = EIGHT;
9 : led_seg = NINE;
default : led_seg = BLANK;
endcase
end
4'b0100 :
begin
case (led_num3)
0 : led_seg = ZERO+1;
1 : led_seg = ONE+1;
2 : led_seg = TWO+1;
3 : led_seg = THREE+1;
4 : led_seg = FOUR+1;
5 : led_seg = FIVE+1;
6 : led_seg = SIX+1;
7 : led_seg = SEVEN+1;
8 : led_seg = EIGHT+1;
9 : led_seg = NINE+1;
default : led_seg = BLANK;
endcase
end
4'b1000 :
begin
case (led_num4)
0 : led_seg = ZERO;
1 : led_seg = ONE;
2 : led_seg = TWO;
3 : led_seg = THREE;
4 : led_seg = FOUR;
5 : led_seg = FIVE;
6 : led_seg = SIX;
7 : led_seg = SEVEN;
8 : led_seg = EIGHT;
9 : led_seg = NINE;
default : led_seg = BLANK;
endcase
end
default
begin
led_seg = 'hx;
end
endcase
end
endmodule
2.引脚分配源代码，StopWatch.ucf
net led_clk loc = p80; #1KHZ
net led_rst loc = p57;
net pause loc = p59;
net led_sel<3> loc = p3;
net led_sel<2> loc = p5;
net led_sel<1> loc = p7;
net led_sel<0> loc = p9;
net led_seg<7> loc = p14;
net led_seg<6> loc = p16;
net led_seg<5> loc = p18;
net led_seg<4> loc = p21;
net led_seg<3> loc = p23;
net led_seg<2> loc = p27;
net led_seg<1> loc = p30;
net led_seg<0> loc = p33;
设计比较简单，但是亮点不少，主要为：
1.使用XilinxXC2S200型FPGA器件设计实现
2.使用电子EDA实验开发系统的2位拨动开关作为A方向和B方向有车通过的传感器的输入，使用系统的6位发光二级管作为A方向的红绿黄灯和B方向红绿黄灯输出，使用系统的数字时钟作为系统运行的时钟。
3.使用Xilinx ISE 6.3软件进行Verilog HDL开发。
有感兴趣的朋友可以扩展一下，成功的感觉固然喜悦，但是追求成功的感觉，更让人觉得激情昂扬。
