[笔记].算法 - 计数器.[Verilog]
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发表于 8/23/2010 8:34:39 PM
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出自Quartus II自带模板。
1. 二进制计数器
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module binary_counter |
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#(parameter WIDTH=64) |
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( |
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input clk, enable, reset, |
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output reg [WIDTH-1:0] count |
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); |
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|
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// Reset if needed, or increment if counting is enabled |
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always @ (posedge clk or posedge reset) |
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begin |
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if (reset) |
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count <= 0; |
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else if (enable == 1'b1) |
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count <= count + 1; |
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end |
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|
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endmodule |
2. 二进制升降计数器
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module binary_up_down_counter |
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#(parameter WIDTH=64) |
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( |
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input clk, enable, count_up, reset, |
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output reg [WIDTH-1:0] count |
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); |
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|
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// Reset if needed, increment or decrement if counting is enabled |
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always @ (posedge clk or posedge reset) |
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begin |
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if (reset) |
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count <= 0; |
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else if (enable == 1'b1) |
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count <= count + (count_up ? 1 : -1); |
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end |
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|
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endmodule |
3. 饱和限制二进制升降计数器
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module binary_up_down_counter_with_saturation |
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#(parameter WIDTH=32) |
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( |
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input clk, enable, count_up, reset, |
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output reg [WIDTH-1:0] count |
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); |
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|
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reg [WIDTH-1:0] direction; |
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reg [WIDTH-1:0] limit; |
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|
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// Reset if needed, increment or decrement if counter is not saturated |
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always @ (posedge clk or posedge reset) |
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begin |
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if (reset) |
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count <= 0; |
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else if (enable == 1'b1) |
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begin |
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if (count_up) |
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begin |
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direction <= 1; |
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limit <= {WIDTH{1'b1}}; // max value is all 1's |
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end |
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else |
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begin |
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direction <= -1; |
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limit <= {WIDTH{1'b0}}; |
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end |
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|
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if (count != limit) |
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count <= count + direction; |
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end |
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end |
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|
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endmodule |
4. 格雷码计数器
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module gray_counter |
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#(parameter WIDTH=8) |
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( |
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input clk, enable, reset, |
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output reg [WIDTH-1:0] gray_count |
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); |
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|
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// Implementation: |
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|
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// There's an imaginary bit in the counter, at q[-1], that resets to 1 |
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// (unlike the rest of the bits of the counter) and flips every clock cycle. |
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// The decision of whether to flip any non-imaginary bit in the counter |
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// depends solely on the bits below it, down to the imaginary bit. It flips |
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// only if all these bits, taken together, match the pattern 10* (a one |
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// followed by any number of zeros). |
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|
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// Almost every non-imaginary bit has a submodule instance that sets the |
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// bit based on the values of the lower-order bits, as described above. |
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// The rules have to differ slightly for the most significant bit or else |
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// the counter would saturate at it's highest value, 1000...0. |
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|
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// q is the counter, plus the imaginary bit |
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reg q [WIDTH-1:-1]; |
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|
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// no_ones_below[x] = 1 iff there are no 1's in q below q[x] |
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reg no_ones_below [WIDTH-1:-1]; |
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|
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// q_msb is a modification to make the msb logic work |
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reg q_msb; |
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|
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integer i, j, k; |
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|
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always @ (posedge reset or posedge clk) |
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begin |
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if (reset) |
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begin |
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|
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// Resetting involves setting the imaginary bit to 1 |
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q[-1] <= 1; |
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for (i = 0; i <= WIDTH-1; i = i + 1) |
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q[i] <= 0; |
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|
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end |
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else if (enable) |
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begin |
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// Toggle the imaginary bit |
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q[-1] <= ~q[-1]; |
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|
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for (i = 0; i < WIDTH-1; i = i + 1) |
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begin |
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|
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// Flip q[i] if lower bits are a 1 followed by all 0's |
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q[i] <= q[i] ^ (q[i-1] & no_ones_below[i-1]); |
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|
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end |
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|
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q[WIDTH-1] <= q[WIDTH-1] ^ (q_msb & no_ones_below[WIDTH-2]); |
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end |
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end |
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|
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|
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always @(*) |
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begin |
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|
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// There are never any 1's beneath the lowest bit |
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no_ones_below[-1] <= 1; |
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|
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for (j = 0; j < WIDTH-1; j = j + 1) |
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no_ones_below[j] <= no_ones_below[j-1] & ~q[j-1]; |
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|
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q_msb <= q[WIDTH-1] | q[WIDTH-2]; |
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|
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// Copy over everything but the imaginary bit |
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for (k = 0; k < WIDTH; k = k + 1) |
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gray_count[k] <= q[k]; |
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end |
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|
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|
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endmodule |
