[笔记].算法 - 乘积累加器.[Verilog]
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发表于 8/24/2010 12:29:15 PM
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出自Quartus II自带模板。
1. 无符号数乘积累加器
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module unsigned_multiply_accumulate |
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#(parameter WIDTH=8) |
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( |
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input clk, aclr, clken, sload, |
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input [WIDTH-1:0] dataa, |
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input [WIDTH-1:0] datab, |
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output reg [2*WIDTH-1:0] adder_out |
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); |
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// Declare registers and wires |
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reg [WIDTH-1:0] dataa_reg, datab_reg; |
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reg sload_reg; |
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reg [2*WIDTH-1:0] old_result; |
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wire [2*WIDTH-1:0] multa; |
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// Store the results of the operations on the current data |
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assign multa = dataa_reg * datab_reg; |
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// Store the value of the accumulation (or clear it) |
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always @ (adder_out, sload_reg) |
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begin |
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if (sload_reg) |
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old_result <= 0; |
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else |
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old_result <= adder_out; |
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end |
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// Clear or update data, as appropriate |
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always @ (posedge clk or posedge aclr) |
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begin |
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if (aclr) |
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begin |
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dataa_reg <= 0; |
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datab_reg <= 0; |
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sload_reg <= 0; |
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adder_out <= 0; |
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end |
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else if (clken) |
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begin |
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dataa_reg <= dataa; |
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datab_reg <= datab; |
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sload_reg <= sload; |
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adder_out <= old_result + multa; |
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end |
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end |
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endmodule |
2. 有符号数乘积累加器
01 |
module signed_multiply_accumulate |
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#(parameter WIDTH=8) |
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( |
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input clk, aclr, clken, sload, |
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input signed [WIDTH-1:0] dataa, |
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input signed [WIDTH-1:0] datab, |
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output reg signed [2*WIDTH-1:0] adder_out |
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); |
09 |
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// Declare registers and wires |
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reg signed [WIDTH-1:0] dataa_reg, datab_reg; |
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reg sload_reg; |
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reg signed [2*WIDTH-1:0] old_result; |
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wire signed [2*WIDTH-1:0] multa; |
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// Store the results of the operations on the current data |
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assign multa = dataa_reg * datab_reg; |
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// Store (or clear) old results |
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always @ (adder_out, sload_reg) |
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begin |
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if (sload_reg) |
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old_result <= 0; |
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else |
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old_result <= adder_out; |
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end |
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// Clear or update data, as appropriate |
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always @ (posedge clk or posedge aclr) |
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begin |
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if (aclr) |
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begin |
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dataa_reg <= 0; |
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datab_reg <= 0; |
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sload_reg <= 0; |
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adder_out <= 0; |
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end |
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else if (clken) |
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begin |
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dataa_reg <= dataa; |
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datab_reg <= datab; |
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sload_reg <= sload; |
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adder_out <= old_result + multa; |
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end |
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end |
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endmodule |
3. 四乘积累加器
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module sum_of_four_multiply_accumulate |
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#(parameter INPUT_WIDTH=18, parameter OUTPUT_WIDTH=44) |
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( |
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input clk, ena, |
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input [INPUT_WIDTH-1:0] dataa, datab, datac, datad, |
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input [INPUT_WIDTH-1:0] datae, dataf, datag, datah, |
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output reg [OUTPUT_WIDTH-1:0] dataout |
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); |
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// Each product can be up to 2*INPUT_WIDTH bits wide. |
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// The sum of four of these products can be up to 2 bits wider. |
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wire [2*INPUT_WIDTH+1:0] mult_sum; |
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// Store the results of the operations on the current inputs |
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assign mult_sum = (dataa * datab + datac * datad) + (datae * dataf + datag * datah); |
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// Store the value of the accumulation |
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always @ (posedge clk) |
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begin |
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if (ena == 1) |
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begin |
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dataout <= dataout + mult_sum; |
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end |
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end |
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endmodule |
4. 带异步复位的四乘积累加器
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module sum_of_four_multiply_accumulate_with_asynchronous_reset |
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#(parameter INPUT_WIDTH=18, parameter OUTPUT_WIDTH=44) |
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( |
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input clk, ena, aclr, |
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input [INPUT_WIDTH-1:0] dataa, datab, datac, datad, |
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input [INPUT_WIDTH-1:0] datae, dataf, datag, datah, |
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output reg [OUTPUT_WIDTH-1:0] dataout |
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); |
09 |
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// Each product can be up to 2*INPUT_WIDTH bits wide. |
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// The sum of four of these products can be up to 2 bits wider. |
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wire [2*INPUT_WIDTH+1:0] mult_sum; |
13 |
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// Store the results of the operations on the current inputs |
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assign mult_sum = (dataa * datab + datac * datad) + (datae * dataf + datag * datah); |
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// Store the value of the accumulation |
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always @ (posedge clk) |
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begin |
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if (ena == 1) |
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begin |
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dataout <= ((aclr == 1) ? 0 : dataout) + mult_sum; |
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end |
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end |
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endmodule |
