[原创].基于SyntaxHighlighter的Verilog HDL高亮组件.[Verilog]
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发表于 6/23/2010 9:49:57 PM
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引子
一直在用PreCode Snppnet在Liver Writer中处理代码高亮；用起来蛮方便的。但是没有我喜欢的Verilog HDL的高亮。今天我在loydsen的启发下，决定写个基于SyntaxHighlighter的Verilog HDL组件，其实很简单。目前还在整理期间，一些关键字和函数还没有加入，还请各位长辈、行家多提意见和建议。
源代码
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/* |
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* Name: SyntaxHighlighter.brushes.Verilog |
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* Author: Yuphone Chang |
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* Email: yuphone@qq.com/ |
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* Create Date: 5.17, 2010 |
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*/ |
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|
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SyntaxHighlighter.brushes.Verilog = function() |
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{ |
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var datatypes = 'reg integar unsigned ' + |
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'wire tri wand triand tri0 tri1 supply0 supply1 trireg ' + |
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'parameter specparam defparam event '; |
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|
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var primitives = 'and nand or nor xor xnor ' + |
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'buf not ' + |
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'bufif0 bufif1 notif0 notif1 ' |
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'pullup pulldown ' + |
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'pmos rpmos nmos rnmos '; |
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|
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var keywords = 'module endmodule ' + |
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'input output inout ' + |
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'begin end ' + |
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'assign deassign always initial genvar ' + |
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'forever repeat disable wait ' + |
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'function endfunction' + |
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'task endtask ' + |
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'generate endgenerate ' + |
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'specify endspecify ' + |
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'posedge negedge ' + |
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'if else for while ' + |
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'case casex casez endcase default ' + |
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'include timescale ' + |
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'ifdef endif ' + |
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'celldefine endcelldefine ' + |
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'attribute ' |
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'fork join '; |
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|
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var functions = 'display displayb displayo displayh ' + |
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'write writeb writeo writeh ' + |
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'strobe strobeb strobeh strobeo ' + |
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'monitor monitorb monitoro monitorh ' + |
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'fopen fclose ' + |
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'readmemb readmemh ' + |
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'finish stop ' + |
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'time stime realtime timeformat ' + |
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'printtimescale ' + |
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'setup hold setuphold skew recovery period width '; |
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|
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this.regexList = [ |
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// one line comments |
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{ regex: SyntaxHighlighter.regexLib.singleLineCComments,css: 'comments' }, |
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// multiline comments |
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{ regex: SyntaxHighlighter.regexLib.multiLineCComments, css: 'comments' }, |
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// double quoted strings |
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{ regex: SyntaxHighlighter.regexLib.doubleQuotedString, css: 'string' }, |
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// single quoted strings |
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{ regex: SyntaxHighlighter.regexLib.singleQuotedString, css: 'string' }, |
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// constants |
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{ regex: new RegExp("[0-9]+['][bBoOdDhHeEfFtT][0-9a-fA-FzZxX_]+", 'g'), css: 'constants' }, |
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// datatypes |
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{ regex: new RegExp(this.getKeywords(datatypes), 'gm'), css: 'color1 bold' }, |
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// primitives |
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{ regex: new RegExp(this.getKeywords(primitives), 'gm'), css: 'color2 bold' }, |
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// keywords |
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{ regex: new RegExp(this.getKeywords(keywords), 'gm'), css: 'keyword bold' }, |
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// functions |
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{ regex: new RegExp(this.getKeywords(functions), 'gm'), css: 'functions bold' } |
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]; |
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}; |
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|
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SyntaxHighlighter.brushes.Verilog.prototype = new SyntaxHighlighter.Highlighter(); |
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SyntaxHighlighter.brushes.Verilog.aliases = ['verilog', 'v']; |
如何使用
1. 在博客园——管理——设置——页首Html代码中添加以下代码。
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<!--SyntaxHighlighter的核心脚步--> |
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<script type="text/javascript" src="http://files.cnblogs.com/yuphone/shCore.js"></script> |
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<!--自定义的SyntaxHighlighter的Verilog高亮--> |
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<script type="text/javascript" src="http://files.cnblogs.com/yuphone/shVerilogEnhanced.js"></script> |
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<!--SyntaxHighlighter的核心样式表--> |
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<link type="text/css" rel="stylesheet" href="http://files.cnblogs.com/yuphone/shCore.css"> |
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<!--SyntaxHighlighter的默认主题样式表--> |
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<link type="text/css" rel="stylesheet" href="http://files.cnblogs.com/yuphone/shThemeDefault.css"> |
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<!--打开SyntaxHighlighter高亮--> |
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<script type="text/javascript"> |
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SyntaxHighlighter.all(); |
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</script> |
注：此处的的shCore.js、shCore.css和shThemeDefault.css为必需组件，shVerilogEnhanced.js是我自定义Verilog高亮组件。
2. 在Liver Writer或博客园的在线编辑器上，切换到HTML模式，加上pre标签，即可实现Verilog高亮。
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<pre class="brush:v;"> |
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module water_led( |
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input CLOCK_50, // 板载时钟50MHz |
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input Q_KEY, // 板载按键RST |
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output [8:1] LED // LED[1] ~ LED[8] |
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); |
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</pre> |
测试代码
water_led.v
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module water_led( |
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input CLOCK_50, // 板载时钟50MHz |
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input Q_KEY, // 板载按键RST |
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output [8:1] LED // LED[1] ~ LED[8] |
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); |
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|
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//++++++++++++++++++++++++++++++++++++++ |
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// 分频部分 开始 |
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//++++++++++++++++++++++++++++++++++++++ |
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reg [23:0] cnt; // 计数子 |
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|
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// 溢出后自动重新计数 |
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always @ (posedge CLOCK_50, negedge Q_KEY) |
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if (!Q_KEY) |
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cnt <= 0; |
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else |
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cnt <= cnt + 1'b1; |
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|
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wire led_clk = cnt[23]; // 每(2^24/50M = 0.3355)sec取一次 |
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//-------------------------------------- |
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// 分频部分 结束 |
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//-------------------------------------- |
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|
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|
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//++++++++++++++++++++++++++++++++++++++ |
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// 流水灯部分 开始 |
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//++++++++++++++++++++++++++++++++++++++ |
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reg [8:1] led_r; // 定义输出寄存器 |
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reg dir; // 循环方向控制 |
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|
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always @ (posedge led_clk, negedge Q_KEY) |
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if (!Q_KEY) // 复位后右移 |
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dir <= 0; |
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else |
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// 到达左右端点否？到达则换向 |
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if(led_r == 8'h7F && dir == 0) |
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dir <= 1; |
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else if(led_r == 8'h01 && dir == 1) |
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dir <= 0; |
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|
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always @ (posedge led_clk, negedge Q_KEY) |
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if (!Q_KEY) // 复位后右移 |
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led_r <= 8'h01; |
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else |
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// 根据dir，左右移位 |
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// 注意：LED实际移位方向与led_r移位方向相反 |
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// 因为开发板上LED[1]在左，LED[8]在右 |
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if(!dir) |
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led_r <= (led_r << 1) + 1'b1; // LED右移；加法比移位的运算优先级高 |
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else |
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led_r <= (led_r >> 1); // LED左移 |
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|
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// 为什么要取反？ |
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// 因为开发板上的LED是送0亮，送1灭 |
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assign LED = ~led_r; // 寄存器输出 |
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//-------------------------------------- |
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// 流水灯部分 结束 |
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//-------------------------------------- |
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|
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endmodule |
