在看到7.9.3节时，书中讲了一个简化版式的交通信号灯实例，
就照着意思在ISE平台上输入了整个源码，并进行仿真，

思想基本OK，如果只是学习verilog，已基本结束，但我想把实例综合一下，
发现始终报错，出错的地方为: repeat (`Y2RDELAY) @(posedge clock);

发现延迟不可被综合，可实例中又要用到这个功能，我就开始研究如何才能延迟，
最后实现思想如下：（利用case结构实现单级延迟，）
                case (stateChgDelay) // @(posedge clock)
                  DELAY0: ;               
                  DELAY1: stateChgDelay = DELAY0;
                  DELAY2: stateChgDelay = DELAY1;
                  DELAY3: stateChgDelay = DELAY2;
                  DELAY4: stateChgDelay = DELAY3;
                  DELAY5: stateChgDelay = DELAY4;
                  DELAY6: stateChgDelay = DELAY5;
                  default: stateChgDelay = DELAY0;
                endcase
对于任意延迟，再定义一个     reg [3:0] stateSetDelay;
设置stateSetDelay值为要等待的时间，并将上述结构进行变形，
变形后如下：
                case (stateChgDelay)
                  DELAY0: begin
                            case(stateSetDelay)
                                  DELAY0: ;
                                  DELAY1: stateChgDelay = DELAY1;
                                  DELAY2: stateChgDelay = DELAY2;
                                  DELAY3: stateChgDelay = DELAY3;
                                  DELAY4: stateChgDelay = DELAY4;
                                  DELAY5: stateChgDelay = DELAY5;             
                                  DELAY6: stateChgDelay = DELAY6;
                                  default:;                                 
                                endcase
                            end                 
                  DELAY1: stateChgDelay = DELAY0;
                  DELAY2: stateChgDelay = DELAY1;
                  DELAY3: stateChgDelay = DELAY2;
                  DELAY4: stateChgDelay = DELAY3;
                  DELAY5: stateChgDelay = DELAY4;
                  DELAY6: stateChgDelay = DELAY5;
                  default: stateChgDelay = DELAY0;
                endcase
这样即可实现想要的延迟，
附参数定义:
    parameter DELAY0 = 4'd0,
               DELAY1 = 4'd1,
               DELAY2 = 4'd2,
               DELAY3 = 4'd3,
               DELAY4 = 4'd4,
               DELAY5 = 4'd5,
               DELAY6 = 4'd6;