#define HC_RD_REV_REG						(0x00)
#define HC_RD_CTRL_REG						(0x01)
#define HC_WR_CTRL_REG						(0x80+0x01)
#define HC_RD_CMD_STAT_REG					(0x02)
#define HC_WR_CMD_STAT_REG					(0x80+0x02)
#define HC_RD_INTT_STAT_REG					(0x03)
#define HC_WR_INTT_STAT_REG					(0x80+0x03)
#define HC_RD_INTT_ENB_REG					(0x04)
#define HC_WR_INTT_ENB_REG					(0x80+0x04)
#define HC_RD_INTT_DSB_REG					(0x05)
#define HC_WR_INTT_DSB_REG					(0x80+0x05)

#define HC_RD_FRM_INT_REG					(0x0d)
#define HC_WR_FRM_INT_REG					(0x80+0x0d)
#define HC_RD_FRM_REM_REG					(0x0e)
#define HC_WR_FRM_REM_REG					(0x80+0x0e)
#define HC_RD_FRM_NUM_REG					(0x0f)
#define HC_WR_FRM_NUM_REG					(0x80+0x0f)
#define HC_RD_LST_TH_REG					(0x11)
#define HC_WR_LST_TH_REG					(0x80+0x11)

#define HC_RD_RH_DTA_REG					(0x12)
#define HC_WR_RH_DTA_REG					(0x80+0x12)
#define HC_RD_RH_DTB_REG					(0x13)
#define HC_WR_RH_DTB_REG					(0x80+0x13)
#define HC_RD_RH_STAT_REG					(0x14)
#define HC_WR_RH_STAT_REG					(0x80+0x14)
#define HC_RD_RH_PSTAT1_REG					(0x15)
#define HC_WR_RH_PSTAT1_REG					(0x80+0x15)
#define HC_RD_RH_PSTAT2_REG					(0x16)
#define HC_WR_RH_PSTAT2_REG					(0x80+0x16)

#define HC_RD_HW_CFG_REG					(0x20)
#define HC_WR_HW_CFG_REG					(0x80+0x20)
#define HC_RD_DMA_CFG_REG					(0x21)
#define HC_WR_DMA_CFG_REG					(0x80+0x21)
#define HC_RD_TS_CNT_REG					(0x22)
#define HC_WR_TS_CNT_REG					(0x80+0x22)
#define HC_RD_UP_INTT_REG					(0x24)
#define HC_WR_UP_INTT_REG					(0x80+0x24)
#define HC_RD_UP_INTT_ENB_REG				(0x25)
#define HC_WR_UP_INTT_ENB_REG				(0x80+0x25)

#define HC_RD_CHIP_ID_REG					(0x27)
#define HC_RD_SCRATCH_REG					(0x28)
#define HC_WR_SCRATCH_REG					(0x80+0x28)
#define HC_WR_SW_RST_REG					(0x80+0x29)

#define HC_RD_BUF_STAT_REG					(0x2c)
#define HC_WR_BUF_STAT_REG					(0x80+0x2c)
#define HC_RD_DIR_ADDR_LEN_REG				(0x32)
#define HC_WR_DIR_ADDR_LEN_REG				(0x80+0x32)
#define HC_RD_DIR_ADDR_DATA_REG				(0x45)
#define HC_WR_DIR_ADDR_DATA_REG				(0x80+0x45)

#define HC_RD_ISTL_BUF_SZ_REG				(0x30)
#define HC_WR_ISTL_BUF_SZ_REG				(0x80+0x30)
#define HC_RD_ISTL0_BUF_PORT_REG			(0x40)
#define HC_WR_ISTL0_BUF_PORT_REG			(0x80+0x40)
#define HC_RD_ISTL1_BUF_PORT_REG			(0x42)
#define HC_WR_ISTL1_BUF_PORT_REG			(0x80+0x42)
#define HC_RD_ISTL_TG_RATE_REG				(0x47)
#define HC_WR_ISTL_TG_RATE_REG				(0x80+0x47)

#define HC_RD_INTL_BUF_SZ_REG				(0x33)
#define HC_WR_INTL_BUF_SZ_REG				(0x80+0x33)
#define HC_RD_INTL_BUF_PORT_REG				(0x43)
#define HC_WR_INTL_BUF_PORT_REG				(0x80+0x43)
#define HC_RD_INTL_BLK_SZ_REG				(0x53)
#define HC_WR_INTL_BLK_SZ_REG				(0x80+0x53)
#define HC_RD_INTL_PTD_DONE_MAP_REG			(0x17)
#define HC_RD_INTL_PTD_SKIP_MAP_REG			(0x18)
#define HC_WR_INTL_PTD_SKIP_MAP_REG			(0x80+0x18)
#define HC_RD_INTL_LAST_PTD_REG				(0x19)
#define HC_WR_INTL_LAST_PTD_REG				(0x80+0x19)
#define HC_RD_INTL_CURR_ACT_PTD_REG			(0x1a)

#define HC_RD_ATL_BUF_SZ_REG				(0x34)
#define HC_WR_ATL_BUF_SZ_REG				(0x80+0x34)
#define HC_RD_ATL_BUF_PORT_REG				(0x44)
#define HC_WR_ATL_BUF_PORT_REG				(0x80+0x44)
#define HC_RD_ATL_BLK_SZ_REG				(0x54)
#define HC_WR_ATL_BLK_SZ_REG				(0x80+0x54)
#define HC_RD_ATL_PTD_DONE_MAP_REG			(0x1b)
#define HC_RD_ATL_PTD_SKIP_MAP_REG			(0x1c)
#define HC_WR_ATL_PTD_SKIP_MAP_REG			(0x80+0x1c)
#define HC_RD_ATL_LAST_PTD_REG				(0x1d)
#define HC_WR_ATL_LAST_PTD_REG				(0x80+0x1d)
#define HC_RD_ATL_CURR_ACT_PTD_REG			(0x1e)
#define HC_RD_ATL_PTD_DONE_TH_CNT_REG		(0x51)
#define HC_WR_ATL_PTD_DONE_TH_CNT_REG		(0x80+0x51)
#define HC_RD_ATL_PTD_DONE_TH_TIMEOUT_REG	(0x52)
#define HC_WR_ATL_PTD_DONE_TH_TIMEOUT_REG	(0x80+0x52)