所 谓边沿检测， 就是检测输入信号， 或者FPGA内部逻辑信号的跳变， 即上
升沿或者下降沿的检测。这在FPGA电路设计中相当的广泛，今天偶然看到这个知识，想要记录下来以便以后查询。本设计为了防止抖动加了几级触发器。使得信号更稳定。

   module edge_tech_design
(
input clk,
input rst_n,
input trigger,
output pos_edge,
output neg_edge
);
//Capture the rising_endge & falling_edge
reg trigger_r0,trigger_r1,trigger_r2;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
trigger_r0 <= 1'b0;
trigger_r1 <= 1'b0;
trigger_r2 <= 1'b0;
end
else
begin
trigger_r0 <= trigger;
trigger_r1 <= trigger_r0;
trigger_r2 <= trigger_r1;
end
end
assign pos_edge = trigger_r1 & ~trigger_r2;
assign neg_edge = ~trigger_r1 & trigger_r2