AD0809 FPGA实现的程序：（VHDL）
0赞LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY AD0809 IS
PORT( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK,EOC: IN STD_LOGIC;
CLOCK:IN STD_LOGIC;
ALE,START,OE,LOCK0: OUT STD_LOGIC;
DOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END AD0809;
ARCHITECTURE behav OF AD0809 IS
TYPE states IS (st0,st1,st2,st3,st4);
SIGNAL current_state,next_state:states:=st0;
SIGNAL REGL :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK :STD_LOGIC;
SIGNAL CNT1:STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL A :INTEGER RANGE 0 TO 1;
SIGNAL LOWDATA:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL HIGHDATA:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL LOWLED7S:STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL HIGHLED7S:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
LOCK0<=LOCK;
PROCESS(REGL)
BEGIN
LOWDATA<=REGL(3 DOWNTO 0);
HIGHDATA<=REGL(7 DOWNTO 4);
CASE LOWDATA IS
WHEN "0000" => LOWLED7S<="0111111";
WHEN "0001" => LOWLED7S<="0000110";
WHEN "0010" => LOWLED7S<="1011011";
WHEN "0011" => LOWLED7S<="1001111";
WHEN "0100" => LOWLED7S<="1100110";
WHEN "0101" => LOWLED7S<="1101101";
WHEN "0110" => LOWLED7S<="1111101";
WHEN "0111" => LOWLED7S<="0000111";
WHEN "1000" => LOWLED7S<="1111111";
WHEN "1001" => LOWLED7S<="1101111";
WHEN "1010" => LOWLED7S<="1110111";
WHEN "1011" => LOWLED7S<="1111100";
WHEN "1100" => LOWLED7S<="0111001";
WHEN "1101" => LOWLED7S<="1011110";
WHEN "1110" => LOWLED7S<="1111001";
WHEN "1111" => LOWLED7S<="1110001";
WHEN OTHERS => Null;
END CASE;
CASE HIGHDATA IS
WHEN "0000" => HIGHLED7S<="0111111";
WHEN "0001" => HIGHLED7S<="0000110";
WHEN "0010" => HIGHLED7S<="1011011";
WHEN "0011" => HIGHLED7S<="1001111";
WHEN "0100" => HIGHLED7S<="1100110";
WHEN "0101" => HIGHLED7S<="1101101";
WHEN "0110" => HIGHLED7S<="1111101";
WHEN "0111" => HIGHLED7S<="0000111";
WHEN "1000" => HIGHLED7S<="1111111";
WHEN "1001" => HIGHLED7S<="1101111";
WHEN "1010" => HIGHLED7S<="1110111";
WHEN "1011" => HIGHLED7S<="1111100";
WHEN "1100" => HIGHLED7S<="0111001";
WHEN "1101" => HIGHLED7S<="1011110";
WHEN "1110" => HIGHLED7S<="1111001";
WHEN "1111" => HIGHLED7S<="1110001";
WHEN OTHERS => Null;
END CASE;
END PROCESS;
PROCESS(CLOCK)
BEGIN
IF CLOCK'EVENT AND CLOCK='1' THEN CNT1<=CNT1+1;
END IF;
END PROCESS;
PROCESS(CNT1)
BEGIN
CASE CNT1 IS
WHEN "0" =>SEL<="111"; A<=0;
WHEN "1" =>SEL<="110"; A<=1;
WHEN OTHERS =>NULL;
END CASE;
END PROCESS;
PROCESS(A)
BEGIN
CASE A IS
WHEN 0 =>DOUT<=LOWLED7S;
WHEN 1 =>DOUT<=HIGHLED7S;
WHEN OTHERS =>NULL;
END CASE;
END PROCESS;
COM: PROCESS(current_state,EOC)
BEGIN
CASE current_state IS
WHEN st0=>ALE<='0';START<='0';LOCK<='1';OE<='0';next_state<=st1;
WHEN st1=>ALE<='1';START<='0';LOCK<='1';OE<='0';next_state<=st2;
WHEN st2=>ALE<='0';START<='1';LOCK<='0';OE<='0';
IF (EOC='1') THEN next_state<=st3;
ELSE next_state<=st2;
END IF;
WHEN st3=>ALE<='0';START<='0';LOCK<='0';OE<='1';next_state<=st4;
WHEN st4=>ALE<='0';START<='0';LOCK<='1';OE<='1';next_state<=st0;
WHEN OTHERS=>next_state<=st0;
END CASE;
END PROCESS COM;
REG: PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN current_state<=next_state;
END IF;
END PROCESS REG;
LATCH1: PROCESS(LOCK)
BEGIN
IF LOCK='1' AND LOCK'EVENT THEN REGL<=D;
END IF;
END PROCESS LATCH1;
END behav;
