FPGA学习二~~LCD1602显示
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说明一下 我用的是Actel的A3PO30板 晶振是48M的 程序解释得很详细
这个是LCD1602的显示程序 主要是动态机的应用 能够实现动态机保持时间的变化
module yejin(clk,
reset,
lcd_rs,
lcd_rw,
lcd_e,
lcd_d);
input clk,reset;
output lcd_rs;
output lcd_rw;
output lcd_e;
output [7:0]lcd_d;
reg lcd_rs,lcd_e;
reg [7:0]lcd_d;
assign lcd_rw=0;
reg [19:0]delay_count;
reg [19:0]num_count;
parameter state1=24'b0000_0000_0000_0000_0000_0001;
parameter state2=24'b0000_0000_0000_0000_0000_0010;
parameter state3=24'b0000_0000_0000_0000_0000_0100;
parameter state4=24'b0000_0000_0000_0000_0000_1000;
parameter state5=24'b0000_0000_0000_0000_0001_0000;
parameter state6=24'b0000_0000_0000_0000_0010_0000;
parameter state7=24'b0000_0000_0000_0000_0100_0000;
parameter state8=24'b0000_0000_0000_0000_1000_0000;
parameter state9=24'b0000_0000_0000_0001_0000_0000;
parameter state10=24'b0000_0000_0000_0010_0000_0000;
parameter state11=24'b0000_0000_0000_0100_0000_0000;
parameter state12=24'b0000_0000_0000_1000_0000_0000;
parameter state13=24'b0000_0000_0001_0000_0000_0000;
parameter state14=24'b0000_0000_0010_0000_0000_0000;
parameter state15=24'b0000_0000_0100_0000_0000_0000;
parameter state16=24'b0000_0000_1000_0000_0000_0000;
parameter state17=24'b0000_0001_0000_0000_0000_0000;
parameter state18=24'b0000_0010_0000_0000_0000_0000;
parameter state19=24'b0000_0100_0000_0000_0000_0000;
parameter state20=24'b0000_1000_0000_0000_0000_0000;
parameter state21=24'b0001_0000_0000_0000_0000_0000;
parameter state22=24'b0010_0000_0000_0000_0000_0000;
parameter state23=24'b0100_0000_0000_0000_0000_0000;
reg [23:0]state;
reg state_change;
always@(posedge clk or negedge reset)
begin
if(!reset)
begin
state_change<=1'b0;
delay_count<=1'b1;
end
else
if(delay_count==num_count-1)
begin
state_change<=1'b1;
delay_count<=1'b1;
end
else
begin
state_change<=1'b0;
delay_count<=delay_count+1'b1;
end
end
always@(posedge state_change or negedge reset)
begin
if(!reset)
begin
state<=state1;
num_count<=20'd750000; //大概15ms
end
else
begin
case(state)
state1:
begin
state<=state2;
num_count<=20'd4; //大概80ns
lcd_rs<=1'b0;
lcd_e<=1'b0;
lcd_d<=8'b0011_1000;
end
state2:
begin
state<=state3;
num_count<=20'd12; ////大概240ns
lcd_e<=1'b1;
end
state3:
begin
state<=state4;
num_count<=20'd5000; //大概10us
lcd_e<=1'b0;
end
state4:
begin
state<=state5;
num_count<=20'd4;
lcd_d<=8'b0000_1100;
end
state5:
begin
state<=state6;
num_count<=20'd12;
lcd_e<=1'b1;
end
state6:
begin
state<=state7;
num_count<=20'd5000;
lcd_e<=1'b0;
end
state7:
begin
state<=state8;
num_count<=20'd4;
lcd_d<=8'b0000_0110;
end
state8:begin
state<=state9;
num_count<=20'd12;
lcd_e<=1'b1;
end
state9:begin
state<=state10;
num_count<=20'd5000;
lcd_e<=1'b0;
end
state10:begin
state<=state11;
num_count<=20'd4;
lcd_d<=8'b0000_0001;
end
state11:begin
state<=state12;
num_count<=20'd12;
lcd_e<=1'b1;
end
state12:begin
state<=state13;
num_count<=20'd5000;
lcd_e<=1'b0;
end
state13:begin
state<=state14;
num_count<=20'd2000;
end
state14:begin
state<=state15;
num_count<=20'd4;
lcd_rs<=1'b0;
lcd_e<=1'b0;
lcd_d<=8'b10000000;
end
state15:begin
state<=state16;
num_count<=20'd12;
lcd_e<=1'b1;
end
state16:begin
state<=state17;
num_count<=20'd5000;
lcd_e<=1'b0;
end
state17:begin
state<=state18;
num_count<=20'd4;
lcd_rs<=1'b1;
lcd_d<=8'b0100_0001;
end
state18:begin
state<=state19;
num_count<=20'd12;
lcd_e<=1'b1;
end
state19:begin
state<=state20;
num_count<=20'd5000;
lcd_e<=1'b0;
end
state20:begin
state<=state21;
num_count<=20'd4;
lcd_d<=8'b0100_1011;
end
state21:begin
state<=state22;
num_count<=20'd12;
lcd_e<=1'b1;
end
state22:begin
state<=state23;
num_count<=20'd5000;
lcd_e<=1'b0;
end
state23:begin
state<=state14;
num_count<=20'd800;
end
default:begin
state<=state1;
num_count<=20'd800;
end
endcase
end
end
endmodule
