我司研制针对集成相干接收机芯片的驱动电路，采用25GHz高速PCB板材制作而成，设计支持100Gbps PM-QPSK,200Gbps PM-16QAM，PM-OFDM等调制格式，采用12V单电源供电，包含集成相干接收机芯片在内功耗1.2W，交叉点、增益独立可调整，采用免焊接40Ghz带宽SMA射频座，针对空间光大气湍流信道提供快速自适应功率控制功能，详细见论文“Hardware-Efficient Imperfection Compensation for Coherent Receiver Frontend”。

图1. 研制的集成相干接收机驱动电路（焊接华为ICR芯片）

图2. 研制的集成相干接收机驱动电路集成在实时相干光通信接收样机中

其他评估测试及指标参数

Fig. 3. Experimental setup for 2.5-GBaud SP-16QAM transmission with detailed DSP block. (DAC, digital-to-analog converter; EDFA, erbium-doped fiber amplifier; ICR, integrated coherent receiver; PC, polarization controller; LO, local oscillator; VOA, variable optical attenuator).

Fig. 4. Gain control voltages of (a) XI and (b) XQ versus block number with different initial voltages at OSNR = 6.6 dB (FEC Limit). (c) The estimated phase imbalance factor, , versus block number with 3 different tests at OSNR=6.6 dB. One block contains  samples.