Explore: Higher placer effort in detail placement and post-placement optimization.
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WLDrivenBlockPlacement: Wirelength-driven placement of RAM and DSP blocks.
Override timing-driven placement by directing the Placer to minimize the distance of
connections to and from blocks.
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LateBlockPlacement: Defers detailed placement of RAMB and DSP blocks to the final
stages of placement. Normally blocks are committed to valid sites early in the
placement process. Instead, the Placer uses coarse block placements that may not align
with proper columns, then places blocks at valid sites during detail placement.

ExtraNetDelay_high: Increases estimated delay of high fanout and long-distance nets.
Three levels of pessimism are supported: high, medium, and low. ExtraNetDelay_high
applies the highest level of pessimism.
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ExtraNetDelay_medium: Increases estimated delay of high fanout and long-distance
nets.  Three levels of pessimism are supported: high, medium, and low.
ExtraNetDelay_medium applies the default level of pessimism.
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ExtraNetDelay_low: Increases estimated delay of high fanout and long-distance nets. 
Three levels of pessimism are supported: high, medium, and low. ExtraNetDelay_low
applies the lowest level of pessimism.
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SpreadLogic_high: Spreads logic throughout the device. Three levels are supported:
high, medium, and low. SpreadLogic_high achieves the highest level of spreading.
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SpreadLogic_medium: Spreads logic throughout the device. Three levels are
supported: high, medium, and low. SpreadLogic_medium achieves a nominal level of
spreading.
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SpreadLogic_low: Spreads logic throughout the device. Three levels are supported:
high, medium, and low. SpreadLogic_low achieves a minimal level of spreading.
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ExtraPostPlacementOpt: Higher placer effort in post-placement optimization.
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SSI_ExtraTimingOpt: Use an alternate algorithm for timing-driven partitioning across
SLRs.
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SSI_SpreadSLLs: Partition across SLRs and allocate extra area for regions of higher
connectivity.
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SSI_BalanceSLLs: Partition across SLRs while attempting to  balance SLLs between
SLRs.
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SSI_BalanceSLRs: Partition across SLRs to balance number of cells between SLRs.
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SSI_HighUtilSLRs: Force the placer to attempt to place logic closer together in each
SLR.
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RuntimeOptimized: Run fewest iterations, trade higher design performance for faster
runtime.
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Quick: Absolute, fastest runtime, non-timing-driven, performs the minimum required
for a legal design.
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Default: Run place_design with default settings.