From: EETimes.com


PORTLAND, Ore. — Copper interconnections on CMOS could become a bottleneck as future chips get faster. One solution could be harnessing carbon nanotubes, which have much higher electron mobility. Until now, however, researchers have been unable to perfect a method for coaxing the nanoscale carbon tubes into the correct positions on chips.

Now, one group thinks they have the answer.

The world's first CMOS circuit using nanotubes as an interconnect was recently designed at Stanford University, in cooperation with Toshiba Corp. I t was fabricated by Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). The 256 ring oscillators on the 11,000- transistor chip ran at 1 GHz, rivaling the speed of other advanced CMOS chips (the iPhone's processor runs at 700 MHz).

"A lot of research labs are working toward using nanotubes to interconnect chips since they have higher electron mobility than copper, and can be grown much smaller. But ours is the first working digital chip to run at commercial speeds of 1 gigahertz," said electrical engineering professor Philip Wong, a professor of electrical engineering at Stanford.

' The chip was designed as a array of ring oscillators with one missing connection. By adding a nanotube to complete the circuit, the chip demonstrated the viability of nanotubes as a substitute for copper wiring. The nanotubes used were multiwalled types measuring five microns in length and from 50 to 100 nanometers in diameter (about the same size as copper wires). Future versions could use single-walled nanotube wires as small as 1 nm in diameter. The chip measured one hundredth of a square inch.

To simplify fabrication and testing of the ring oscillator array, multiplexing circuitry was provided on the chip so that individual ring oscillators could be separately addressed. The nanotubes were placed in the gap to complete the circuit of a ring oscillator using a novel method that floated a solution over the chip suspending thousands of free-floating nanotubes.

Then an alternating current was supplied to the ring oscillators, which attracted the floating nanotubes to precisely the correct gaps in the circuitry. Once a nanotube snapped into place to bridge a particular gap, the AC signal was turned off for that ring oscillator. The solution was then removed and the chip allowed to dry off.

The work was performed with the help of Stanford University electrical engineering doctoral candidate Gael Close, Toshiba engineers Shinichi Yasuda and Shinobu Fujita along with engineeer Bipul Paul of Toshiba America Research (San Jose, Calif.).

The research was funded by Toshiba, the Interconnect Focus Center, Semiconductor Research Corp. and Close's Intel Graduate Fellowship.

中文版： http://www.eetchina.com/ART_8800505684_480201_NT_fabb7d6f.HTM

* 什么是碳纳米管？
1991年日本NEC公司的饭岛纯雄(Sumio Iijima)首次利用电子显微镜观察到中空的碳纤维，直径一般在几纳米到几十个纳米之间，长度为数微米，甚至毫米，称为“碳纳米管”。理论分析和实验观察认为它是一种由六角网状的石墨烯片卷成的具有螺旋周期管状结构。正是由于饭岛的发现才真正引发了碳纳米管研究的热潮和近十年来碳纳米管科学和技术的飞速发展。 按照石墨烯片的层数，可分为： 1) 单壁碳纳米管（Single-walled nanotubes, SWNTs）：由一层石墨烯片组成。单壁管典型的直径和长度分别为0.75～3nm和1～50μm。又称富勒管(Fullerenes tubes)。 2) 多壁碳纳米管（Multi-walled nanotubes, MWNTs）：含有多层石墨烯片。形状象个同轴电缆。其层数从2～50不等，层间距为0.34±0.01nm，与石墨层间距(0.34nm)相当。多壁管的典型直径和长度分别为2～30nm和0.1～50μm。