The transition from to mesa device topology was motivated by the following issues with the transferred substrate process.

The dominate failure mechanism associated with the TS-process have to do with the substrate removal steps. After the device and circuit formation is complete, BCB coasts the wafer and vias are etched for the subsequent electroplating of a 5um thick ground plane. At this point a GaAS or AlN carrier wafer was soldered against the ground plane. Often the BCB cracks because of the high temperature and pressure experienced by the wafer from the soldering bonder, or pockets of air get trapped between the InP host and carrier wafer. In the areas where this occurs, device and circuit yield is zero. The final step requires the InP host to be etched away. Some-times during this etch, the NiCr resistors are attacked because their SiN protection layer has formed cracks or voids earlier in the process. Circuits using these resistors would not bias correctly.

Device heat-sinking must be considered as the active HBT layers are scaled because the operating power density increases proportional to the device bandwidth squared. In the TS-topology, heat generated in the HBT is removed from the collector contact and Si3N4 dielectric on the emitter contact. Both the heat-sinking mechanisms have high thermal resistance. The triple-mesa topology alleviates this issue because heat generated in the collector can be removed into the high thermally conductive InP substrate.

For the TS-HBT process, device interconnects are deposited before and after the InP host wafer is removed. Electrical connection between them is required. To make this possible and have passivated HBTs, the passivation dielectric (polyimide) is pattern-etched leaving the device encapsulated while clearing the field. This requires the device interconnect metal climb ~0.8um over the device encapsulation. The metal at the interconnect step coverage sites is thin and necessitates a much lower maximum operating current density (mA/um) for them.

By using a mesa HBT technology the first two issues are avoided, greatly improving HBT performance and yield. Other failure mechanisms associated with emitter-base lift-off short-circuits, excessive emitter semiconductor undercut, and metal interconnect step coverage fractures and current handling were still unresolved, as shown in Fig. 3.1. Because of these mesa process limitations, discrete device yield was poor for highly scaled devices with emitter widths less than 0.7um, and for those with a collector to emitter mesa width ratio less than three. For circuits using large device features, the yield was poor for transistor count greater than 100 HBTs. As this chapter will report, numerous fabrication improvements and changes have been made to the mesa HBT process flow for increased device scaling and increased circuit yield employing such devices.



Richard: 转移衬底还是有一些问题。