It's an ultra-high speed Direct Digital frequency-Synthesizer (DDS) with clock frequency of more than 5GHz. The architecture is ROM-less with a sine-weighted nonlinear DAC insteading of the traditional ROM for phase-magnitude convertion. While this can improve the speed of taotal DDS circuit, it can't give as high SFDR as ROM-with architecture does. However, look at the output wave, with 5GHz clock frequency and Frequency-Control-Word of 1, the simulation result show a well-look 19.53125MHz sine-wave. The worst spur locates at 664.0625MHz as predicted. As the theory predicts, it give a SFDR of 30.663dBc. Everything seems OK except the duration it cost my computer to run this circuit simulation. Given below is the evidence.




20281s= 338m=5.6h. Oh my Jordan, 5.6 hours! And the layout work will be a much more horrible thing