Chapter 6: Layout

Questions:

1. MMIC layout data files are built up from lines or polygons?

2. What does hierarchy mean in the context of MMIC layout?

3. Does the MMIC designer construct the layers within the transistors?

4. What is the consequence if critical errors are not spotted before the masks are manufactured?

5. What determines the layout rules? Give two examples. What is the general approach for laying out an MMIC?

6. What do DRC, LVS and ERC stand for?

7. What is the process of arraying?

8. What is the PCM, and where is it placed?

Answers:

1. Polygons.

2. Hierarchy means that a group of individually defined polygons (on any number of layers) can be grouped into one object known as a cell. The cell can then be copied and reproduced at many points in the layout, and the link to the original cell is retained so that when it is changed, all copies are changed as well.

3. No, the foundry supplies the complete transistor layouts, and these are just connected together with transmission lines by the MMIC designer.

4. Large amounts of time and money will be wasted before the error is brought to light by nonfunctioning designs found during RF-On-Wafer testing.

5. The processing methods and technology determine the layout rules. For example, a mesa isolation process requires that all FET gates be parallel to each other so that the gate feed lines are fabricated up a positive slope of the mesa, and closed structures cannot be made with metal layers because they do not fabricate cleanly when using a lift-off process.

6. DRC stands for design-rule-checking, LVS stands for layout-versus-schematic checking, and ERC stands for electrical-rule-checking.

7. Arraying is the process of taking multiple MMIC design layouts and constructing an orthogonal array or reticule of the designs.

8. PCMs are the process control monitors, and they are placed within the drop-in arrays.