#define ADF70XX_COM  PORTB  
#define ADF70XX_PIN  PINB  
#define ADF7020_SDATA  4
#define ADF7020_SCLK 2
#define ADF7020_SLE  1
#define ADF7020_CE  0

volatile  unsigned char ADF70XX_ONOFF ;

struct
    {
        unsigned long  reg;
        unsigned char  data[4];    // Warning: Be endian-specific when accessing bytes

    } ADF70XX_REG;
   
void ADF70XX_writereg(unsigned char * reg_bytes)
{
    signed char i, j;
    unsigned char byte;

    ADF70XX_COM &= ~(_BV(ADF7020_SLE));
    ADF70XX_COM &= ~_BV(ADF7020_SCLK);

    /* Clock data out MSbit first */

    for (i=3; i>=0; i--)
    {
        byte = reg_bytes[i];

        for (j=8; j>0; j--)
        {
            ADF70XX_COM &= ~_BV(ADF7020_SCLK);
            if ((byte & 0x80)==0x80)
        {
         ADF70XX_COM |= 1<<ADF7020_SDATA;
         }
            else
        {
         ADF70XX_COM &= ~_BV(ADF7020_SDATA);
         }
   
   
            ADF70XX_COM |= _BV(ADF7020_SCLK);
            byte += byte;
        }
        ADF70XX_COM &= ~_BV(ADF7020_SCLK);
    }

    ADF70XX_COM |= _BV(ADF7020_SLE);
    ADF70XX_COM |= _BV(ADF7020_SLE);
    ADF70XX_COM &= ~_BV(ADF7020_SDATA);
    ADF70XX_COM &= ~(_BV(ADF7020_SLE));
}

ADF70XX_REG ADF70XX_readreg(unsigned char cfg_data)
{
    ADF70XX_REG reg_value;
    unsigned char i, j;
    unsigned char byte;

 

    reg_value.reg = ((cfg_data & 0x1F) << 4);
    reg_value.reg |= 0x07;

    ADF70XX_writereg((unsigned char *)&reg_value);

    reg_value.reg = 0;

    /* Read back value */

    ADF70XX_COM &= ~_BV(ADF7020_SDATA);
    ADF70XX_COM &= ~_BV(ADF7020_SCLK);
    ADF70XX_COM |= _BV(ADF7020_SLE);
    ADF70XX_COM |= _BV(ADF7020_SCLK);
    byte = 0;
    ADF70XX_COM &= ~_BV(ADF7020_SCLK);

    for (i=2; i<=3; i++)
    {
        for (j=8; j>0; j--)
        {
            ADF70XX_COM |= _BV(ADF7020_SCLK);
            byte += byte;
            ADF70XX_COM &= ~_BV(ADF7020_SCLK);
          if ((PINA&0x02)==0x02) byte |= 1;
        }

        reg_value.byte[i] = byte;

  _delay_ms(10); 
       
 }//for i=2 : 3;

 ADF70XX_COM |= _BV(ADF7020_SCLK);
 ADF70XX_COM &= ~_BV(ADF7020_SCLK);
  ADF70XX_COM &= ~(_BV(ADF7020_SLE));

  return reg_value;
}

//ce 为低有效
void ADF70XX_Power_on(void)
{
 if (ADF70XX_PIN&0X01== 0)
 {
  ADF70XX_COM |= _BV(ADF7020_CE);
  ADF70XX_ONOFF=1;
  _delay_ms(100); //delay
 }
}

void dd_set_TX_mode()
{
 ADF70XX_REG reg_value;

 //write R1, turn on VCO
 reg_value.whole_reg = 0x00535011;
 ADF70XX_writereg(&reg_value.byte[0]);
 _delay_ms(10);

 //write R3, turn on TX/RX clocks
 reg_value.whole_reg = 0x2B1734E3;
 ADF70XX_writereg(&reg_value.byte[0]);

 //write R0, turn on PLL
 reg_value.whole_reg = 0x015F3820;
 ADF70XX_writereg(&reg_value.byte[0]);
 _delay_ms(10);  

 //write R2, turn on PA
 reg_value.whole_reg = 0x00685582;   //Ramp Rate = 16 codes/bit, TX level = 2;
// reg_value.whole_reg = 0x006FF582;   //max power TX
 ADF70XX_writereg(&reg_value.byte[0]);
 if (is_internal_PA_ramp_used == TRUE)  _delay_ms(100); //delay for 4ms, 4 bits for DR = 1Kbps

}
void dd_set_RX_mode()
{
 ADF70XX_REG reg_value;

 //write R1, turn on VCO
 reg_value.whole_reg = 0x00535011;
 ADF70XX_writereg(&reg_value.byte[0]);

 //write R3, turn on TX/RX clocks
 reg_value.whole_reg = 0x2B1734E3;
 ADF70XX_writereg(&reg_value.byte[0]);

 //write R5 to start IF filter cal
 reg_value.whole_reg = 0x00003155; //write R5 to start IF filter cal
 ADF70XX_writereg(&reg_value.byte[0]);
 _delay_ms(10); 

 //write R11, configure sync word detect
 reg_value.whole_reg = 0x091A2B3B; //sync word = 0x123456;
 ADF70XX_writereg(&reg_value.byte[0]);

 //write R12, start sync word detect
 reg_value.whole_reg = 0x0000018C; //for sync word detect;
 ADF70XX_writereg(&reg_value.byte[0]);

 //write R0, turn on PLL
 reg_value.whole_reg = 0x095F2DC0;
 ADF70XX_writereg(&reg_value.byte[0]);
 _delay_ms(10);  

 //write R4, turn on demodulation
 reg_value.whole_reg = 0x8016AA14;
 ADF70XX_writereg(&reg_value.byte[0]);

 if (is_ADF7020_AFC_ON == TRUE)
 {
  //write R10, turn AFC on
  reg_value.whole_reg = 0x3296355A;
  ADF70XX_writereg(&reg_value.byte[0]);
 }

}

 ps:附件为官方驱动