这部分将直接用VHDL语言编写。正弦波的产生方法为查表法，主程序如下：

1. process(clk)

begin

if(clk'event and clk='1') then

    if q=128 then

     q<=0;

else

     q<=q+1;

end if;

end if;

end process;

1. process(q)

begin

case q is

when 00=>d<=127;when 01=>d<=133;when 02=>d<=139;when 03=>d<=146;

when 04=>d<=152;when 05=>d<=158;when 06=>d<=164;when 07=>d<=170;

when 08=>d<=176;when 09=>d<=181;when 10=>d<=187;when 11=>d<=192;

when 12=>d<=198;when 13=>d<=203;when 14=>d<=208;when 15=>d<=212;

when 16=>d<=217;when 17=>d<=221;when 18=>d<=225;when 19=>d<=229;

when 20=>d<=233;when 21=>d<=236;when 22=>d<=239;when 23=>d<=242;

when 24=>d<=244;when 25=>d<=247;when 26=>d<=249;when 27=>d<=250;

when 28=>d<=252;when 29=>d<=253;when 30=>d<=253;when 31=>d<=254;

when 32=>d<=254;when 33=>d<=254;when 34=>d<=253;when 35=>d<=253;

when 36=>d<=252;when 37=>d<=250;when 38=>d<=249;when 39=>d<=247;

when 40=>d<=244;when 41=>d<=242;when 42=>d<=239;when 43=>d<=236;

when 44=>d<=233;when 45=>d<=229;when 46=>d<=225;when 47=>d<=221;

when 48=>d<=217;when 49=>d<=212;when 50=>d<=208;when 51=>d<=203;

when 52=>d<=198;when 53=>d<=192;when 54=>d<=187;when 55=>d<=181;

when 56=>d<=176;when 57=>d<=170;when 58=>d<=164;when 59=>d<=158;

when 60=>d<=152;when 61=>d<=146;when 62=>d<=139;when 63=>d<=133;

when 64=>d<=127;when 65=>d<=121;when 66=>d<=115;when 67=>d<=108;

when 68=>d<=102;when 69=>d<=96;when 70=>d<=90;when 71=>d<=84;

when 72=>d<=78;when 73=>d<=73;when 74=>d<=67;when 75=>d<=62;

when 76=>d<=56;when 77=>d<=51;when 78=>d<=46;when 79=>d<=42;

when 80=>d<=37;when 81=>d<=33;when 82=>d<=29;when 83=>d<=25;

when 84=>d<=21;when 85=>d<=18;when 86=>d<=15;when 87=>d<=12;

when 88=>d<=10;when 89=>d<=7;when 90=>d<=5;when 91=>d<=4;

when 92=>d<=2;when 93=>d<=1;when 94=>d<=1;when 95=>d<=0;

when 96=>d<=0;when 97=>d<=0;when 98=>d<=1;when 99=>d<=1;

when 100=>d<=2;when 101=>d<=4;when 102=>d<=5;when 103=>d<=7;

when 104=>d<=10;when 105=>d<=12;when 106=>d<=15;when 107=>d<=18;

when 108=>d<=21;when 109=>d<=25;when 110=>d<=29;when 111=>d<=33;

when 112=>d<=37;when 113=>d<=42;when 114=>d<=46;when 115=>d<=51;

when 116=>d<=56;when 117=>d<=62;when 118=>d<=67;when 119=>d<=73;

when 120=>d<=78;when 121=>d<=84;when 122=>d<=90;when 123=>d<=96;

when124=>d<=102;when125=>d<=108;when126=>d<=115;

when127=>d<=121;when 128=>d<=127;

when others=>null;

end case;

end process;

在1）中当clk时钟每来个上升沿，q加一然后在2）中查表然后输出值。2）中的数值是根据正弦波一个周期抽样点而来的，抽样点为128，正弦信号的频率是由输入频率决定的。其模块框图如下：