high impedance, low capacitance, ground-referenced, free from glitches, impervious to overdrive
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发表于 5/15/2012 10:07:35 AM
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Understand Signal Pipelining and Synchronization
To understand the nature of FIFO designs, it is important to understand how pipelining is
used to maximize performance and implement synchronization logic for clock-domain
crossing. Data written into the write interface may take multiple clock cycles before it can be accessed on the read interface
| Psalm 139:13-14“For you created my inmost being; you knit me together in my mother’s womb. I praise you because I am fearfully and wonderfully made; your works are wonderful, I know that full well.” |
