256数据包抓包
0赞`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/08/24 10:11:33
// Design Name:
// Module Name: select_package
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module select_package(
input rd_clk ,
input rst_n ,
input [ 5:0] fifo_rd_len_cp ,
input [ 7:0] cs_i ,
input [ 63:0] rd_data_in ,
output rd_en ,
output [ 63:0] data_out,
output dataout_trig
);
reg [8:0] package_cnt=8'b0 ;
reg rd_trig_1 ;
reg rd_trig ;
reg [ 1:0] cur_state ;
reg [ 1:0] next_state ;
reg [ 5:0] trig_cnt ;
reg [ 5:0] data_cnt =6'b0 ;
reg rd_en_1 ;
reg [63:0] data_out_1 ;
reg dataout_trig_1;
wire rd_trig_n ;
parameter idle = 4'd0 ,
one = 4'd1 ;
assign rd_en = rd_en_1 ;
assign data_out = data_out_1 ;
assign dataout_trig = dataout_trig_1 ;
always @(posedge rd_clk or negedge rst_n)
if (!rst_n)
rd_trig <= 1'b0 ;
else if(fifo_rd_len_cp>=8'd32)
rd_trig <= 1'b1 ;
else
rd_trig <= 1'b0 ;
always @(posedge rd_clk or negedge rst_n)
if (!rst_n)
rd_trig_1 <= 1'b0 ;
else
rd_trig_1 <= rd_trig ;
assign rd_trig_n = (rd_trig == 1'b1) && (rd_trig_1 == 1'b0) ;
always @(posedge rd_clk or negedge rst_n)
if (!rst_n)
cur_state <= idle ;
else
cur_state <= next_state ;
always @(negedge rd_clk )
case(cur_state)
idle: begin
rd_en_1 <= 1'b0;
if (rd_trig_n)
begin
next_state<= one ;
package_cnt <=package_cnt + 1'b1 ;
trig_cnt<=1'b0;
end
else
if(package_cnt==9'd256)
package_cnt <=1'b0;
end
one : if (!rd_trig_n)
begin
if (trig_cnt==8'd32)
begin
trig_cnt<=1'b0;
next_state<=idle;
rd_en_1<= 1'b0;
end
else
begin
trig_cnt<= trig_cnt+1'b1;
rd_en_1<=1'b1;
next_state<= one ;
end
end
default : next_state <= idle ;
endcase
always @(negedge rd_clk )
if (!rst_n)
begin
dataout_trig_1<=1'b0;
data_out_1 <= 64'b0;
end
else
if ((package_cnt == cs_i+1'b1)&&(rd_en_1==1'b1))
begin
data_cnt<=data_cnt+1'b1;
data_out_1 <= rd_data_in ;
dataout_trig_1<=1'b1;
end
else
if(data_cnt==6'd32)
begin
data_cnt<=6'b0;
dataout_trig_1<=1'b0;
end
endmodule
