[Zed使用心得]PS是怎样把时钟传递给PL的？
0赞
发表于 12/19/2012 9:54:42 PM
阅读（9046）
问题：
今天几个同事在讨论一个问题：新建IP核时候一般是把Bus2IP_Clk直接当做自己的逻辑代码的时钟，但这个时钟到底是怎样和PS联系起来的呢？
如下图所示，从XPS来看，IP核的时钟端口是S_AXI_ACLK，来自ps的FCLK_CLK0，这个时钟可以自己配置。
![VE5FUUWGXM4VLR]EBNY5RPL](http://files.chinaaet.com/images/2012/12/19/6461281071318.jpg "VE5FUUWGXM4VLR]EBNY5RPL")
但从IP核的顶层文件vga.vhd中无法直观地看出S_AXI_ACLK和Bus2IP_Clk有什么联系，这就导致了上述问题的出现。
分析：
这里又要分析代码了，仍以之前教程里的vga IP 核为例（工程文件的下载已经提供）。user_logic.vhd就不用多说了，和接口无关，而且是最底层的元件，时钟信号来自上层的vga.vhd，分析一下vga.vhd：
vga.vhd
------------------------------------------------------------------------------ -- Filename: vga.vhd -- Version: 1.00.a -- Description: Top level design, instantiates library components and user logic. -- Date: Thu Dec 13 19:27:14 2012 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library axi_lite_ipif_v1_01_a; use axi_lite_ipif_v1_01_a.axi_lite_ipif; library vga_v1_00_a; use vga_v1_00_a.user_logic; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width -- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width -- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size -- C_USE_WSTRB -- AXI4LITE slave: Write Strobe -- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout -- C_BASEADDR -- AXI4LITE slave: base address -- C_HIGHADDR -- AXI4LITE slave: high address -- C_FAMILY -- FPGA Family -- C_NUM_REG -- Number of software accessible registers -- C_NUM_MEM -- Number of address-ranges -- C_SLV_AWIDTH -- Slave interface address bus width -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- S_AXI_ACLK -- AXI4LITE slave: Clock -- S_AXI_ARESETN -- AXI4LITE slave: Reset -- S_AXI_AWADDR -- AXI4LITE slave: Write address -- S_AXI_AWVALID -- AXI4LITE slave: Write address valid -- S_AXI_WDATA -- AXI4LITE slave: Write data -- S_AXI_WSTRB -- AXI4LITE slave: Write strobe -- S_AXI_WVALID -- AXI4LITE slave: Write data valid -- S_AXI_BREADY -- AXI4LITE slave: Response ready -- S_AXI_ARADDR -- AXI4LITE slave: Read address -- S_AXI_ARVALID -- AXI4LITE slave: Read address valid -- S_AXI_RREADY -- AXI4LITE slave: Read data ready -- S_AXI_ARREADY -- AXI4LITE slave: read addres ready -- S_AXI_RDATA -- AXI4LITE slave: Read data -- S_AXI_RRESP -- AXI4LITE slave: Read data response -- S_AXI_RVALID -- AXI4LITE slave: Read data valid -- S_AXI_WREADY -- AXI4LITE slave: Write data ready -- S_AXI_BRESP -- AXI4LITE slave: Response -- S_AXI_BVALID -- AXI4LITE slave: Resonse valid -- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready ------------------------------------------------------------------------------ entity vga is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer := 8; C_BASEADDR : std_logic_vector := X"FFFFFFFF"; C_HIGHADDR : std_logic_vector := X"00000000"; C_FAMILY : string := "virtex6"; C_NUM_REG : integer := 1; C_NUM_MEM : integer := 1; C_SLV_AWIDTH : integer := 32; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here axi_hs : out std_logic; axi_vs : out std_logic; axi_red : out std_logic_vector(3 downto 0); axi_green : out std_logic_vector(3 downto 0); axi_blue : out std_logic_vector(3 downto 0); -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; attribute SIGIS of S_AXI_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_ARESETN : signal is "Rst"; end entity vga; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of vga is constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address ); constant USER_SLV_NUM_REG : integer := 1; constant USER_NUM_REG : integer := USER_SLV_NUM_REG; constant TOTAL_IPIF_CE : integer := USER_NUM_REG; constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space ); ------------------------------------------ -- Index for CS/CE ------------------------------------------ constant USER_SLV_CS_INDEX : integer := 0; constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; ------------------------------------------ -- IP Interconnect (IPIC) signal declarations ------------------------------------------ signal ipif_Bus2IP_Clk : std_logic; signal ipif_Bus2IP_Resetn : std_logic; signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); signal ipif_Bus2IP_RNW : std_logic; signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0); signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0); signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); signal ipif_IP2Bus_WrAck : std_logic; signal ipif_IP2Bus_RdAck : std_logic; signal ipif_IP2Bus_Error : std_logic; signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0); signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0); signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0); signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; begin ------------------------------------------ -- instantiate axi_lite_ipif ------------------------------------------ AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif generic map ( C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH, C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_RREADY => S_AXI_RREADY, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_AWREADY => S_AXI_AWREADY, Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Addr => ipif_Bus2IP_Addr, Bus2IP_RNW => ipif_Bus2IP_RNW, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_CS => ipif_Bus2IP_CS, Bus2IP_RdCE => ipif_Bus2IP_RdCE, Bus2IP_WrCE => ipif_Bus2IP_WrCE, Bus2IP_Data => ipif_Bus2IP_Data, IP2Bus_WrAck => ipif_IP2Bus_WrAck, IP2Bus_RdAck => ipif_IP2Bus_RdAck, IP2Bus_Error => ipif_IP2Bus_Error, IP2Bus_Data => ipif_IP2Bus_Data ); ------------------------------------------ -- instantiate User Logic ------------------------------------------ USER_LOGIC_I : entity vga_v1_00_a.user_logic generic map ( -- MAP USER GENERICS BELOW THIS LINE --------------- --USER generics mapped here -- MAP USER GENERICS ABOVE THIS LINE --------------- C_NUM_REG => USER_NUM_REG, C_SLV_DWIDTH => USER_SLV_DWIDTH ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ --USER ports mapped here -- 底层端口 => 顶层端口 hsync => axi_hs, vsync => axi_vs, red => axi_red, green => axi_green, blue => axi_blue, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_RdCE => user_Bus2IP_RdCE, Bus2IP_WrCE => user_Bus2IP_WrCE, IP2Bus_Data => user_IP2Bus_Data, IP2Bus_RdAck => user_IP2Bus_RdAck, IP2Bus_WrAck => user_IP2Bus_WrAck, IP2Bus_Error => user_IP2Bus_Error ); ------------------------------------------ -- connect internal signals ------------------------------------------ ipif_IP2Bus_Data <= user_IP2Bus_Data; ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; ipif_IP2Bus_Error <= user_IP2Bus_Error; user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0); user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0); end IMP;
由vga.vhd的源码可以看出，在例化user_logic时，将Bus2IP_Clk端口连接到了ipif_Bus2IP_Clk这跟信号线上；vga.vhd还例化了一个axi_lite_ipif模块，该模块的Bus2IP_Clk端口也连接到了ipif_Bus2IP_Clk。 除此之外就没有和ipif_Bus2IP_Clk有联系的信号了，在XPS中也找不到其他线索。那么想知道两个Bus2IP_Clk到底有什么区别最好的方法莫过于查看axi_lite_ipif的源文件。到了这里，我就联想到IP核结构的相关知识了，前几天我在分析IP核结构的时候，曾经分析过编译时用到哪些资源是在pao文件中指定的，这些资源的存储路径是在prj文件中指定的。所以查看一下prj文件：
_vga_xst.prj
vhdl proc_common_v3_00_a "D:/ProTools/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" vhdl proc_common_v3_00_a "D:/ProTools/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" vhdl proc_common_v3_00_a "D:/ProTools/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" vhdl proc_common_v3_00_a "D:/ProTools/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" vhdl proc_common_v3_00_a "D:/ProTools/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" vhdl proc_common_v3_00_a "D:/ProTools/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" vhdl proc_common_v3_00_a "D:/ProTools/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" vhdl axi_lite_ipif_v1_01_a "D:/ProTools/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/address_decoder.vhd" vhdl axi_lite_ipif_v1_01_a "D:/ProTools/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd" vhdl axi_lite_ipif_v1_01_a "D:/ProTools/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/axi_lite_ipif.vhd" vhdl vga_v1_00_a "../hdl/vhdl/user_logic.vhd" vhdl vga_v1_00_a "../hdl/vhdl/vga.vhd"
可以看到和axi_lite_ipif相关的有三个文件，分别为：address_decoder.vhd，axi_lite_ipif.vhd，slave_attachment.vhd。分别打开查看一下和Bus2IP_Clk相关的内容，发现Bus2IP_Clk是模块slave_attachment的输出端口，来源于S_AXI_ACLK。文件中相关语句如下：
![R87U(}N]QX}JVHN)%]B~D(9](http://files.chinaaet.com/images/2012/12/19/6461313688134.jpg "R87U(}N]QX}JVHN)%]B~D(9")
axi_lite_ipif.vhd是axi_lite_ipif IP核的顶层文件，这个文件对slave_attachment模块进行了例化：
![_HX$2)K6]1Q%G@AZRCW97$P](http://files.chinaaet.com/images/2012/12/19/6461342694966.jpg "_HX$2)K6]1Q%G@AZRCW97$P")
分析到这，我想下面也不用再多说了，其实看到slave_attachment.vhd中的Bus2IP_Clk <= S_AXI_ACLK;相信大家就明白了，其实Bus2IP_Clk和S_AXI_ACLK是一回事。至于S_AXI_ACLK和PS时钟的连接在XPS中可以直观的看出来,这一点在问题提出的时候，已经给过图示了。
结论：
最后，总结一下整个过程：PS.FCLK_CLK0 –> VGA.S_AXI_ACLK –> axi_lite_ipif.S_AXI_ACLK –> slave_attachment.S_AXI_ACLK –> slave_attachment.Bus2IP_Clk –> axi_lite_ipif.Bus2IP_Clk –> user_logic.Bus2IP_Clk
版权声明：
本文由博主“cuter”发布。欢迎转载，但不得擅自更改博文内容，也不得用于任何盈利目的。转载时不得删除作者简介和版权声明。如有盗用而不说明出处引起的版权纠纷，由盗用者自负。
博客官方地址：
ChinaAET：http://blog.chinaaet.com/cuter521
