vivado中的propagated clock

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When use report_clocks, it outputs some info list below:


  P: Propagated

  G: Generated

  V: Virtual

  I: Inverted


What does propagated mean? I find it belongs to the clock generated by MMCM and the source clock.   What does Virtual mean? When and how to use Virtual clock?


SDC are synopsys design constraints. This is the constraint mechanism that is used by Vivado, but is actually a open standard for constraints. The report_clocks output is "standard" among different tools, including ASIC tools...

The letter P signifies a propagated clock. A non-propagated clock is an ideal clock (which would not have the P) - this would be used to model a clock that has an "ideal" clock insertion - where the clock arrives at all destinations of the clock with no propagation delay. This concept is used in ASIC designs (prior to clock insertion), but would never really apply in an FPGA (all clocks inside the FPGA should be propagated).

A virtual clock is a clock created with a create_clock command that is not attached to any design objects - i.e. you don't specify any ports, pins, or nets to apply the clock to in the create_clock command. Such a clock would be used only for the purposes of constraining your design - usually for the purpose of having a "virtual" clock to reference for set_input_delay and set_output_delay commands.