工作地点上海，具体如下：

1.       Sr. Analog Design Engineer

Accountabilities:

²  Develop novel analog/mixed signal integrated circuit IPs for high performance FPGA chip.

²  Candidate will focus on analog or mix signal design for high performance, high speed input and output circuit, DDR phy circuit, high speed serdes, PLL, oscillator, BGR...

²  Development task starts from specification to final IP release. Detail work includes design spec, circuit architecture and implementation, pre-layout and post-layout simulation, behavior modeling, IP integration and silicon bring up and debug.

Qualifications:

²  MS or PhD Degree in Electrical Engineering with an emphasis in analog or mixed signal design

²  5 years of experience in analog or mixed signal IP development under advanced CMOS process node (65nm and below)

²  Demonstrated strong analog or mixed signal IP design skills in high speed connectivity product development

²  Solid knowledge in analog circuit, signal processing theory and semiconductor device physics

²  Hands on skills in circuit design, simulation, Verilog and Verilog-A behavior modeling

²  Familiar with main stream EDA tools in analog mixed signal design

²  Strong problem analysis and debug skill

²  Experience with one or more following areas: PLL, CDR, CTLE, BGR, DRIVER, IO, DDR, LVDS.

²  Experience working with layout team together and guide layout optimization to achieve high quality layout

²  Experience in product tape out and silicon bring up/debug

²  Ability to multi-tasks and set priorities with tight schedule

²  Experience working in dynamic, fast-paced company environment

²  Good oral and writing English communication skill

2.       Sr. FPGA Circuit Design Engineer

Accountabilities:

²  Responsible for FPGA integration custom IP design Tspec

²  Responsible for schematic ic circuit design and verification

²  Guide layout engineer to finish the IP layout design

²  Responsible for FPGA full-chip group sim (function and timing)

²  Responsible for FPGA full-chip integration

²  Responsible for FPGA bring-up supporting

Qualifications:

²  5+ relative circuit design experience

²  Familiar with digital design logic, clock design, sram design

²  Familiar with Virtuoso / Finesim design and verification tool

²  Familiar with scripts, like Perl / Python / Tcl…

²  Familiar with Verilog / Synthesis / STA

3.       Sr. Fullchip Integration Design Engineer

Accountabilities:

²  Responsible for FPGA integration Tspec

²  Responsible for FPGA integration design, and digital block RTL design

²  Research the schematic IP design for top integration

²  Responsible for timing constraints, synthesis, STA, low power design for digital block level

²  Responsible for dft scan insertion & ATPG for digital block level

²  Co-work with P&R and Layout team for the physical implementation of digital block and full chip

²  Responsible for chip bring up

Qualifications:

²  5+ relative full chip integration experience

²  Digital logic design capability and clock, rst, mbist relative design experience

²  Familiar with ASIC flow, synthesis, STA, DFT..., relative EDA tools

²  Familiar with scripts, like Perl / Python / Tcl…

²  Familiar with Verilog / Synthesis / STA

²  Familiar with Virtuoso / Spice simulation is better

4.       Sr. Digital Design Engineer

Accountabilities:

²  Create module level target specification based on exactly understanding the product requirement and full-chip target specification

²  Independently complete module design and simulation

²  Be responsible for RTL synthesis, Lint rule check and CDC check 

²  Support chip level STA, DFT and P&R

²  Support top level simulation, verification, and post-simulation

²  Support emulation, validation and application

²  Write design document and provide design report

Qualifications:

²  Have about 3-5-year working experience of digital front-end design

²  Master degree in EE or related fields

²  Good fundamental acknowledges in communication, computer and digital signal processing

²  Capability to analyze the design requirement and make best design trade-off

²  Understanding whole digital circuit development flow

²  Be proficient in RTL coding and high level modeling using Verilog language

²  Capability to set up test bench for design simulation and debug

²  Understand timing constraint and timing issue fixing

²  Have experience in synthesis or static timing analysis

²  Have good communication skill in both Chinese and English

5.       Sr. FPGA SW Validation Engineer

Accountabilities:

²  Experienced with the process flow of EDA tools for FPGA

²  Familiar with software testing process and method

²  Write test cases in Verilog/VHDL or C/C++ to verify key features during software development

²  Write scripts to improve the productivity of testing

²  Responsible for Lattice software product validation and verification

²  Responsible for Lattice FPGA product co-verification

²  Responsible for synthesis tool evaluation and testing vs 3rd party vendor

²  Responsible for simulation tool integration testing

²  Execute QA regression on test platform and analyze the failures

²  Identify Software issue, file CRs and keep tracking CRs till being verified

²  Customer issue analysis and isolation

²  Provide QA testing report to support Software release

Qualifications:

²  Bachelor degree with 5 working years or Master degree with 3 working years. Majored in EE/Automation/related major is preferred.

²  Skill in digital logic circuits design with FPGA application

²  Skill in Verilog/VHDL coding

²  Familiar with embedded system

²  Skill in C/C++ coding and debugging

²  Familiar with FPGA technologies, preferably Lattice

²  Experience in applying EDA tools such as Diamond, ISE/Vivado or Quartus II

²  Experience in synthesis tools application as well as simulation tools

²  Experience in script programming (Python, Perl, Tcl or Shell and etc.)

²  Experience in operation system i.e Windows and Linux

²  Good written and verbal communication skills in English

6.       Sr. SOC Design Engineer

Accountabilities:

²  Embedded System (SOC) design and development on Lattice FPGA device

²  Embedded System (SOC) integration and verification

²  Processor (CPU) IP design and verification based on use case requirement

²  System Bus, Peripheral, Interconnect, Debug IP design and verification

²  FPGA Bit file generation and board/system level debug

²  Co-work with software engineer for embedded system setup and debug

Qualifications:

²  Have a master's degree in ME/EE/CS

²  5+ years’ experience in Embedded System (SOC) design or processor design

²  Strong proficiency in Verilog/system Verilog

²  Familiar with simulation tools like Ncsim, modelsim 

²  Familiar with scripts programming (Makefile, Perl, Python etc)

²  Good understanding on system bus (AXI, AHB, Wishbone etc)

²  Experiences in one or more of the following area will be a plus:

a. RISC architecture and micro-architecture (RISC-V, ARM);

b. SOC debug system and JTAG;

c. Peripheral and legacy IP (PCIE, SPI, I2C, UART etc);

d. Embedded programming with C language;

e. ASIC or FPGA design flow;

f. Advanced verification methodology (UVM etc).

²  Must possess independent problem solving skills

²  Strong written and verbal communication skills and the ability to work with multiple groups

²  Must be a sense of responsibility and work actively

7.       Sr. Processor Design Engineer

Accountabilities:

²  Processor (CPU) IP design and verification on Lattice FPGA device

²  SOC integration and verification

²  FPGA Bitfile generation and board/system level debug

²  Co-work with software engineer for embedded system setup and debug

Qualifications:

²  Have a master's degree in ME/EE/CS

²  5+ years’ experience in processor(CPU) design or SOC design

²  Strong proficiency in Verilog/System Verilog

²  Familiar with simulation tools like Ncsim, Modelsim 

²  Familiar with Linux work station environment and script programming (Makefile, Perl, Python etc)

²  Good understanding on system bus (AXI, AHB, Wishbone etc.)

²  Experience in one or more of the following area will be a plus:

·           RISC architecture and micro-architecture (RISC-V, ARM);

·           CPU Core design;

·           CPU platform SOC integration;

·           SOC debug system and JTAG protocol;

·           Cache system design;

·           Advanced verification methodology (UVM etc.).

²  Must possess independent problem solving skills

²  Strong written and verbal communication skills and the ability to work with multiple groups

²  Must be a sense of responsibility and work actively

8.       Sr. System Solution Engineer

Accountabilities:

²  As the key contributor of System Solution team, architect System Level Solution based on Lattice product, to support marketing and customer requirements of different industries through close partnership with Sales and Marketing team.

²  Develop the collateral to promote the solution to customer and develop the related document to guide the solution implementation.

²  As the expert in System solution team, to guide team members and customers for high-speed interface protocol design and application.

²  Work with the cross functional teams to develop System Solution Platform for system level performance analysis.

Qualifications:

²  BS/MS, in Communication, Microelectronics/Electronic Engineering, Compute Science, or relevant subject.

²  BS 7+ or MS 5+ year’s FPGA/ASIC development and debugging experience.

²  Experienced in RTL design and debug, and familiar with simulation tools Modelsim or NC-Verilog.

²  Good knowledge on Serdes, and experienced in high-speed interface protocol is preferred, such as PCIE, HDMI, DP/eDP, and GBE.

²  Experienced in security network of server system, communication network, automotive network, or IoT, is preferred.

²  Expertise in encryption/decryption algorithm, able to lead the team to develop security solution is preferred.

²  Experienced in communication, video bridge and processing, is preferred.

²  Good communication skills in both Chinese and English. Willingness to work with teams in US, Europe, Japan, and Korea.

²  Highly organized, with attention to details, time management, and deadlines. Good team player is expected.