[笔记].算法 - 乘积求和器.[Verilog]
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发表于 8/25/2010 11:14:45 AM
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出自Quartus II自带模板。
1. 四乘积求和器
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module sum_of_four_multipliers |
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#(parameter WIDTH=18) |
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( |
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input clk, ena, |
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input [WIDTH-1:0] dataa, datab, datac, datad, |
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input [WIDTH-1:0] datae, dataf, datag, datah, |
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output reg [2*WIDTH+1:0] dataout |
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); |
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always @ (posedge clk) |
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begin |
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if (ena == 1) |
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begin |
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dataout <= (dataa * datab + datac * datad) + (datae * dataf + datag * datah); |
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end |
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end |
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endmodule |
2. 带流水线寄存器的两乘积求和器
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module sum_of_two_multipliers_pipeline |
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#(parameter WIDTH=16) |
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( |
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input clock, aclr, |
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input [WIDTH-1:0] dataa, datab, datac, datad, |
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output reg [2*WIDTH:0] result |
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); |
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reg [WIDTH-1:0] dataa_reg, datab_reg, datac_reg, datad_reg; |
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reg [2*WIDTH-1:0] mult0_result, mult1_result; |
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always @ (posedge clock or posedge aclr) begin |
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if (aclr) begin |
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dataa_reg <= {(WIDTH){1'b0}}; |
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datab_reg <= {(WIDTH){1'b0}}; |
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datac_reg <= {(WIDTH){1'b0}}; |
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datad_reg <= {(WIDTH){1'b0}}; |
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mult0_result <= {(2*WIDTH){1'b0}}; |
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mult1_result <= {(2*WIDTH){1'b0}}; |
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result <= {(2*WIDTH+1){1'b0}}; |
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end |
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else begin |
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dataa_reg <= dataa; |
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datab_reg <= datab; |
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datac_reg <= datac; |
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datad_reg <= datad; |
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mult0_result <= dataa_reg * datab_reg; |
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mult1_result <= datac_reg * datad_reg; |
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result <= mult0_result + mult1_result; |
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end |
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end |
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endmodule |
3. 扫描链模式的四乘积求和器
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module sum_of_four_multipliers_scan_chain |
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#(parameter WIDTH=18) |
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( |
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input clk, ena, |
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input [WIDTH-1:0] dataa, |
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input [WIDTH-1:0] datab0, datab1, datab2, datab3, |
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output reg [2*WIDTH+1:0] dataout |
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); |
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// Four scan chain registers |
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reg [WIDTH-1:0] a0, a1, a2, a3; |
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always @ (posedge clk) |
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begin |
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if (ena == 1) |
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begin |
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// The scan chain (which mimics the behavior of a shift register) |
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a0 <= dataa; |
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a1 <= a0; |
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a2 <= a1; |
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a3 <= a2; |
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// The order of the operands is important for correct inference |
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dataout <= (a3 * datab3 + a2 * datab2) + (a1 * datab1 + a0 * datab0); |
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end |
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end |
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endmodule |
4. 串连的八乘积求和器
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module sum_of_eight_multipliers_chainout |
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#(parameter WIDTH=18) |
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( |
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input clk, ena, |
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input [WIDTH-1:0] a0, a1, a2, a3, a4, a5, a6, a7, |
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input [WIDTH-1:0] b0, b1, b2, b3, b4, b5, b6, b7, |
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output reg [2*WIDTH+1:0] dataout |
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); |
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// Declare wires |
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wire [2*WIDTH+1:0] sum1, sum2; |
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// Store the results of the first two sums |
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assign sum1 = (a0 * b0 + a1 * b1) + (a2 * b2 + a3 * b3); |
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assign sum2 = (a4 * b4 + a5 * b5) + (a6 * b6 + a7 * b7); |
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always @ (posedge clk) |
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begin |
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if (ena == 1) |
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begin |
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dataout <= sum1 + sum2; |
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end |
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end |
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endmodule |
5. 带广泛的数据通路的两乘积求和器
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module sum_of_two_multipliers_wide_datapath |
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#(parameter WIDTH_A=36, WIDTH_B=18) |
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( |
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input clk, ena, |
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input [WIDTH_A-1:0] a0, a1, |
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input [WIDTH_B-1:0] b0, b1, |
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output reg [WIDTH_A+WIDTH_B:0] dataout |
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); |
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always @ (posedge clk) |
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begin |
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if (ena == 1) |
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begin |
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dataout <= a0 * b0 + a1 * b1; |
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end |
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end |
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endmodule |
