调用Xilinx的时钟IP产生2路输出时钟，直接接IO口出现了问题，综合可以过去，但map就出现

类似

map的时候生成下面的错误。
WARNING:Place:1205 - This design contains a global buffer instance,<U_CLOCK_PLL/clkout2_buf>, driving the net, <dsp_clkin_OBUF>, that is driving the following (first 30) non-clock source pins off chip.
   < PIN: dsp_clkin.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution:

出错的关键是因为时钟输出直接接在I/O上。按照其中的说法：实例化一个ODDR2，这个小元件的详细介绍在xilinx参考文档ug381中有详细介绍。

代码原来是这样的，

TX_PLLS   THE_TX_PLLS
 (// Clock in ports
  .CLK_IN1(txpll_clk),
  // Clock out ports
  .CLK_OUT1(txpll_ck0),
  .CLK_OUT2(txpll_ck1),
  // Status and control signals
  .RESET(txpll_rst),
  .LOCKED(txpll_luk)
 );
 

修改后

wire clk_out1;
wire clk_out2;


 
TX_PLLS   THE_TX_PLLS
 (// Clock in ports
  .CLK_IN1(txpll_clk),
  // Clock out ports
  .CLK_OUT1(clk_out1),
  .CLK_OUT2(clk_out2),
  // Status and control signals
  .RESET(txpll_rst),
  .LOCKED(txpll_luk)
 );
 
 
 //clk_out1
 
 ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment 
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q  
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" 
                   //   set/reset
)
ODDR2_clkout1 (
   .Q(txpll_ck0),   // 1-bit DDR output data
   .C0(clk_out1), // 1-bit clock input
   .C1(~clk_out1), // 1-bit clock input
   .CE(1'b1), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);

//clk_out2 
 
 ODDR2 #(
   // The following parameters specify the behavior
   // of the component.
   .DDR_ALIGNMENT("NONE"), // Sets output alignment 
                           // to "NONE", "C0" or "C1"
   .INIT(1'b0),    // Sets initial state of the Q  
                   //   output to 1'b0 or 1'b1
   .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" 
                   //   set/reset
)
ODDR2_clkout2 (
   .Q(txpll_ck1),   // 1-bit DDR output data
   .C0(clk_out1), // 1-bit clock input
   .C1(~clk_out1), // 1-bit clock input
   .CE(1'b1), // 1-bit clock enable input
   .D0(1'b1), // 1-bit data input (associated with C0)
   .D1(1'b0), // 1-bit data input (associated with C1)
   .R(1'b0),   // 1-bit reset input
   .S(1'b0)    // 1-bit set input
);

就可以了，刚转Xilinx，好多在学习，哎