AD9220关于FPGA数据采集程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ad9220 is            // 定义AD9220采集控制模块的输入输出信号端
  port(       
       reset_n,clk:in std_logic;      
       jdata:in std_logic_vector(11 downto 0);
   jsclk,firclk:out std_logic;   
       ad_caiji:out std_logic_vector(11 downto 0)    
      );
end entity ad9220;
architecture behav of ad9220 is
signal ad_data1,ad_data2:std_logic_vector(11 downto 0); 
signal present_state,next_state:std_logic_vector(2 downto 0);
begin
process(clk,reset_n) // 时钟分频进程，为后续FIR滤波模块提供合适的工作时钟信号
variable  fir_count:std_logic_vector(11 downto 0);  
variable  firclk_ctrl:std_logic;  
begin
	if(reset_n='0') then 
	firclk_ctrl:='0';
		fir_count:=x"000";
	elsif (clk'event and clk='1') then
		fir_count:=fir_count+1;
		if(fir_count = x"0FA") then   
// FIR采集时间计算250*20ns*2 = 5us*2 = 100kHz=1e5
		fir_count:=x"000";
	if(firclk_ctrl='0') then
		firclk_ctrl:='1';
		firclk<='1';
	else
		firclk_ctrl:='0';
		firclk<='0';
	end if;
	end if;
	end if;
end process;
process(clk,reset_n)                        // 数据采集进程
	begin
	if(reset_n='0') then 
		jsclk<='1';
	elsif (clk'event and clk='1') then
	case next_state is
	when "000" =>
		jsclk<='1';
		present_state<="001";
	when "001" =>
		jsclk<='1';
		present_state<="010";
	when "010" =>
		jsclk<='1';
		present_state<="011";
	when "011" =>
		jsclk<='0';
		ad_data1<=jdata;	  
present_state<="100";
	when "100" =>
		jsclk<='0';
		present_state<="101";
	when "101" =>
		jsclk<='0';
		present_state<="110";              // 20
		when "110" =>
		jsclk<='0';
present_state<="111";              // 40
	when "111" =>
	jsclk<='0';
	ad_data2<=jdata;	
	present_state<="000";             // 60 
when others =>
	jsclk<='1';
	present_state<="000";
	end case; 
	end if;
end process;
process(present_state)          // 状态切换进程，对整个采集过程进行管理
	begin
	next_state<=present_state;		
end process;
process(clk)                               // 数据输出进程
	begin
	if (clk'event and clk='0') then
		ad_caiji<=ad_data1;
	end if;
end process;
end architecture behav