【技术分享】双向口的仿真
moduleinout_sim(din,clk,ctrl,dout,dinout);input[3:0]din;inputclk;inputctrl;outputreg[3:0]dout;inout[3:0]dinout;reg[3:0]din_reg;assigndinout=ctrl?din_reg:4'hz;always@(posedgeclk)if(ctrl)din_reg<=din;elsedout<=dinout;endmodule`timescale1ns/1nsmod
发表于 2/25/2013 9:40:03 PM
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