What design language do you use?

There is no prefered language and each designer uses their language of choice.Keep in mind that a core written in a seldom used language will not be very useful.Most designers use either VHDL or Verilog.

What is the preferred System-on-Chip(SoC) bus for opencores?

The preferred bus is WISHBONE.This is the only commonly used SoC bus which is truly free.Rudolf Usselmann has analysed the advantages of the common SoC busses.