The WISHBONE System-on-Chip(SoC) Interconnect Architecture for Portable IPCores is a portable interface for use with semiconductor IPCores.Its purpose is to foster design reuse by alleviating system-on-chip integration problems.This is accomplished by creating a common,logical interface between IPCores.This improves the portability and reliability of the system,and results in faster time-to-market for the end user.WISHBONE itself is not an IPCore...it is a specification for creating IPCores.

OpenCores recommends the WISHBONE System-on-Chip Interconnect as the interface to all cores that require interfacing to other cores inside a chip(FPGA,ASIC,etc.).

The WISHBONE standard is not copyrighted,and is in the public domain.It may be freely copied and distributed by any means. Furthermore,it may be used for the design and production of integrated circuit components without royalties or other financial obligations.