敏感列表，if条件相关的一个问题
0赞错误：cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
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建模的时候这样写会出现这个错误
if(!switch&&!iVS)
begin
for(n=0;n<=256;n=n+1) begin
state_count[n] <= 19'd0;
end
end
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在网上查了半天，发现如果该成这样就可以了
if(!switch)
begin
if(!iVS)
begin
for(n=0;n<=256;n=n+1) begin
state_count[n] <= 19'd0;
end
end
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为什么呢？看官网解释：
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http://www.altera.com.cn/support/kdb/solutions/rd06242003_6128.html
翻译一下：
标题
Error: Verilog HDL Conditional Statement error at <location>: If-Else Statement does not match any sensitivity list edge
verilog 条件声明错误：if-else声明不能match任何一个敏感列表的跳变沿。意会意会啊。。。
说明
This error may occur if you are trying to model a DFF with multiple control signals. The Quartus® II software will only infer a secondary signal from a single secondary signal in an IF condition. For example, you may have written the following sample structure to model a DFF primitive that can be reset by two signals, rst1 or rst2:
你在建一个具有多个控制信号的D触发器的模块时候可能会产生这个错误。（后面这句不会翻译）在if条件句中，Q II 软件只能从一个single secondary 信号中推论出次级信号，比如：你建立了一个可以被两个信号复位的D触发器：
always @ (posedge clk or posedge rst1 or posedge rst2)
begin
if (rst1 == 1'b1 || rst2 == 1'b1)
q <= 1'b0;
else
q <= d;
end
To correct this, edit the design to specify only one edge per if condition. For example, if you were to edit the previous example to specify only one edge per if condition, the Quartus II software would then succesfully recognize the DFF primitive. The sample code would then appear as follows:
为了解决这个问题，写的时候每次if条件只写一个跳变沿，如下：
always @ (posedge clk or posedge rst1 or posedge rst2)
begin
if (rst1 == 1'b1)
q <= 1'b0;
else if (rst2 == 1'b1)
q <= 1'b0;
else
q <= d;
end
最终我的理解是软件太low，我用的版本是11.0，不知道现在解决没有。
