FSM控制
0赞在数据输入结束后立刻流出结果，还是允许延时若干时钟周期后再流出结果，要根据具体的性能要求来决定。
当输入8位全零的数据时，在时钟下一拍就可以得到计算结果。借鉴计算机体系结构中的流水的思想，可以考虑数据一边输入一边送入相关的功能部件进行计算，主要是加法器和乘法器。应该尽可能选择低位数的加法器和乘法器以减少设计成本
always@(present_state or Serial_in)
begin
case(present_state)
State0:
begin
Sel=3'b000;
if(!Serial_in)
Next_state=State0;
else
Next_state=State1;
end
State1:
begin
if(!Serial_in)
Next_state=StateY;
else
Next_state=State2;
end
State2:
begin
if(!Serial_in)
Next_state=StateY;
else
Next_state=State3;
end
State3:
begin
if(!Serial_in)
Next_state=StateY3;
else
Next_state=State4;
end
State4:
begin
if(!Serial_in)
Next_state=StateY4;
else
Next_state=State5;
end
State5:
begin
if(!Serial_in)
Next_state=StateY;
else
Next_state=State5;
end
StateY: //output process
begin
Sel=3'b100;
Next_state=State0;
end
StateY3:
begin
Sel=3'b010;
Next_state=State0;
end
StateY4:
begin
Sel=3'b001;
Next_state=State0;
end
default:
Next_state=State0;
endcase
end
