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Viva~do学习6:Timing概念

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  1. Lunch edge与Capture edge

    Luanch edge:源端Reg发送数据的时钟边沿(参考点

    Capture edge:目的端Reg捕获数据的边沿(Next launch edge)。

  2. 4种时序路径

    1)Input delay:外部Device port到内部Sequential cell路径延时;

    2)Data path delay:内部两个Sequential cell之间的路径延时;

    3)Output delay:内部Sequential到外部Device port路径的延时;

    4)Pin data path delay:Pin之间的延时;

  3. 公式计算

    Data arrival time = Launch edge + Tclka + Tco + Tdata

    Clock arrival time = Capture edge + Tclkb

    Data require time(setup) = Clock arrival time - Tsu - Setup uncentainly

    Data require time(hold) = Clock arrival time(Next)+ Th  + Hold uncentainly

                       (Data的最小有效采样窗口:起点(Tsu) -> 终点(Th))

       Setup slack = Data required time(setup) - Data arrival time

       Hold slack = Data arrival time - Data require time{hold)

                       Setup slack为负数:说明Data path delay太大

                       Hold slack为负数:说明clock的延时太大

4. System

     Tdata = Tlogical + Tnet

     Tsys >= Tco +Tdata + Tsu