【再说FPGA】Note:A gray code
modulegray(inputclk,inputrst_n,outputreg[3:0]gray);reg[3:0]bin;wire[3:0]bnext;wire[3:0]gnext;always@(posedgeclkornegedgerst_n)beginif(!rst_n)beginbin<=0;gray<=0;endelsebeginbin<=bnext;gray<=gnext;endendassignbnext=bin+1;assigngnext=(bnext
发表于 12/28/2012 5:33:24 PM
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