【VIP之旅】FPGA的“特权”流水操作，初步理解
moduletest_Pipelining(inputCLK,inputRSTn,outputreg[7:0]result);reg[7:0]x,y;reg[3:0]i;always@(posedgeCLKornegedgeRSTn)if(!RSTn)beginx<=8'd0;y<=8'd0;i<=4'd0;endelsecase(i)0:beginx<=8'd1;y<=8'd1;i<=i+1'b1;end1:beginx<=8'd2;y<=8'd
发表于 2014/6/16 11:52:03
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